60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*/
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#ifndef __MFD_MT6397_CORE_H__
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#define __MFD_MT6397_CORE_H__
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enum mt6397_irq_numbers {
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MT6397_IRQ_SPKL_AB = 0,
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MT6397_IRQ_SPKR_AB,
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MT6397_IRQ_SPKL,
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MT6397_IRQ_SPKR,
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MT6397_IRQ_BAT_L,
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MT6397_IRQ_BAT_H,
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MT6397_IRQ_FG_BAT_L,
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MT6397_IRQ_FG_BAT_H,
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MT6397_IRQ_WATCHDOG,
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MT6397_IRQ_PWRKEY,
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MT6397_IRQ_THR_L,
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MT6397_IRQ_THR_H,
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MT6397_IRQ_VBATON_UNDET,
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MT6397_IRQ_BVALID_DET,
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MT6397_IRQ_CHRDET,
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MT6397_IRQ_OV,
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MT6397_IRQ_LDO,
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MT6397_IRQ_HOMEKEY,
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MT6397_IRQ_ACCDET,
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MT6397_IRQ_AUDIO,
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MT6397_IRQ_RTC,
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MT6397_IRQ_PWRKEY_RSTB,
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MT6397_IRQ_HDMI_SIFM,
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MT6397_IRQ_HDMI_CEC,
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MT6397_IRQ_VCA15,
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MT6397_IRQ_VSRMCA15,
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MT6397_IRQ_VCORE,
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MT6397_IRQ_VGPU,
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MT6397_IRQ_VIO18,
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MT6397_IRQ_VPCA7,
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MT6397_IRQ_VSRMCA7,
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MT6397_IRQ_VDRM,
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MT6397_IRQ_NR,
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};
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struct mt6397_chip {
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struct device *dev;
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struct regmap *regmap;
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int irq;
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struct irq_domain *irq_domain;
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struct mutex irqlock;
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u16 wake_mask[2];
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u16 irq_masks_cur[2];
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u16 irq_masks_cache[2];
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u16 int_con[2];
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u16 int_status[2];
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};
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#endif /* __MFD_MT6397_CORE_H__ */
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