443 lines
12 KiB
C
443 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cadence WDT driver - Used by Xilinx Zynq
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc.
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*
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#define CDNS_WDT_DEFAULT_TIMEOUT 10
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/* Supports 1 - 516 sec */
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#define CDNS_WDT_MIN_TIMEOUT 1
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#define CDNS_WDT_MAX_TIMEOUT 516
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/* Restart key */
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#define CDNS_WDT_RESTART_KEY 0x00001999
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/* Counter register access key */
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#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000
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/* Counter value divisor */
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#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000
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/* Clock prescaler value and selection */
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#define CDNS_WDT_PRESCALE_64 64
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#define CDNS_WDT_PRESCALE_512 512
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#define CDNS_WDT_PRESCALE_4096 4096
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#define CDNS_WDT_PRESCALE_SELECT_64 1
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#define CDNS_WDT_PRESCALE_SELECT_512 2
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#define CDNS_WDT_PRESCALE_SELECT_4096 3
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/* Input clock frequency */
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#define CDNS_WDT_CLK_10MHZ 10000000
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#define CDNS_WDT_CLK_75MHZ 75000000
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/* Counter maximum value */
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#define CDNS_WDT_COUNTER_MAX 0xFFF
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static int wdt_timeout;
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static int nowayout = WATCHDOG_NOWAYOUT;
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module_param(wdt_timeout, int, 0644);
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MODULE_PARM_DESC(wdt_timeout,
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"Watchdog time in seconds. (default="
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__MODULE_STRING(CDNS_WDT_DEFAULT_TIMEOUT) ")");
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module_param(nowayout, int, 0644);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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/**
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* struct cdns_wdt - Watchdog device structure
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* @regs: baseaddress of device
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* @rst: reset flag
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* @clk: struct clk * of a clock source
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* @prescaler: for saving prescaler value
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* @ctrl_clksel: counter clock prescaler selection
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* @io_lock: spinlock for IO register access
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* @cdns_wdt_device: watchdog device structure
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*
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* Structure containing parameters specific to cadence watchdog.
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*/
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struct cdns_wdt {
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void __iomem *regs;
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bool rst;
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struct clk *clk;
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u32 prescaler;
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u32 ctrl_clksel;
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spinlock_t io_lock;
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struct watchdog_device cdns_wdt_device;
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};
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/* Write access to Registers */
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static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val)
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{
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writel_relaxed(val, wdt->regs + offset);
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}
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/*************************Register Map**************************************/
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/* Register Offsets for the WDT */
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#define CDNS_WDT_ZMR_OFFSET 0x0 /* Zero Mode Register */
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#define CDNS_WDT_CCR_OFFSET 0x4 /* Counter Control Register */
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#define CDNS_WDT_RESTART_OFFSET 0x8 /* Restart Register */
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#define CDNS_WDT_SR_OFFSET 0xC /* Status Register */
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/*
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* Zero Mode Register - This register controls how the time out is indicated
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* and also contains the access code to allow writes to the register (0xABC).
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*/
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#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
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#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */
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#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */
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#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
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#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */
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/*
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* Counter Control register - This register controls how fast the timer runs
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* and the reset value and also contains the access code to allow writes to
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* the register.
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*/
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#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */
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/**
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* cdns_wdt_stop - Stop the watchdog.
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*
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* @wdd: watchdog device
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*
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* Read the contents of the ZMR register, clear the WDEN bit
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* in the register and set the access key for successful write.
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*
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* Return: always 0
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*/
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static int cdns_wdt_stop(struct watchdog_device *wdd)
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{
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struct cdns_wdt *wdt = watchdog_get_drvdata(wdd);
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spin_lock(&wdt->io_lock);
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cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET,
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CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK));
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spin_unlock(&wdt->io_lock);
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return 0;
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}
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/**
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* cdns_wdt_reload - Reload the watchdog timer (i.e. pat the watchdog).
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*
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* @wdd: watchdog device
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*
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* Write the restart key value (0x00001999) to the restart register.
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*
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* Return: always 0
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*/
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static int cdns_wdt_reload(struct watchdog_device *wdd)
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{
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struct cdns_wdt *wdt = watchdog_get_drvdata(wdd);
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spin_lock(&wdt->io_lock);
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cdns_wdt_writereg(wdt, CDNS_WDT_RESTART_OFFSET,
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CDNS_WDT_RESTART_KEY);
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spin_unlock(&wdt->io_lock);
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return 0;
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}
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/**
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* cdns_wdt_start - Enable and start the watchdog.
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*
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* @wdd: watchdog device
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*
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* The counter value is calculated according to the formula:
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* calculated count = (timeout * clock) / prescaler + 1.
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* The calculated count is divided by 0x1000 to obtain the field value
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* to write to counter control register.
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* Clears the contents of prescaler and counter reset value. Sets the
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* prescaler to 4096 and the calculated count and access key
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* to write to CCR Register.
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* Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
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* or Interrupt signal(IRQEN) with a specified cycles and the access
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* key to write to ZMR Register.
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*
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* Return: always 0
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*/
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static int cdns_wdt_start(struct watchdog_device *wdd)
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{
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struct cdns_wdt *wdt = watchdog_get_drvdata(wdd);
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unsigned int data = 0;
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unsigned short count;
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unsigned long clock_f = clk_get_rate(wdt->clk);
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/*
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* Counter value divisor to obtain the value of
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* counter reset to be written to control register.
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*/
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count = (wdd->timeout * (clock_f / wdt->prescaler)) /
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CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;
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if (count > CDNS_WDT_COUNTER_MAX)
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count = CDNS_WDT_COUNTER_MAX;
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spin_lock(&wdt->io_lock);
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cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET,
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CDNS_WDT_ZMR_ZKEY_VAL);
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count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
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/* Write counter access key first to be able write to register */
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data = count | CDNS_WDT_REGISTER_ACCESS_KEY | wdt->ctrl_clksel;
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cdns_wdt_writereg(wdt, CDNS_WDT_CCR_OFFSET, data);
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data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
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CDNS_WDT_ZMR_ZKEY_VAL;
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/* Reset on timeout if specified in device tree. */
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if (wdt->rst) {
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data |= CDNS_WDT_ZMR_RSTEN_MASK;
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data &= ~CDNS_WDT_ZMR_IRQEN_MASK;
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} else {
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data &= ~CDNS_WDT_ZMR_RSTEN_MASK;
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data |= CDNS_WDT_ZMR_IRQEN_MASK;
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}
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cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET, data);
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cdns_wdt_writereg(wdt, CDNS_WDT_RESTART_OFFSET,
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CDNS_WDT_RESTART_KEY);
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spin_unlock(&wdt->io_lock);
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return 0;
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}
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/**
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* cdns_wdt_settimeout - Set a new timeout value for the watchdog device.
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*
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* @wdd: watchdog device
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* @new_time: new timeout value that needs to be set
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* Return: 0 on success
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*
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* Update the watchdog_device timeout with new value which is used when
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* cdns_wdt_start is called.
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*/
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static int cdns_wdt_settimeout(struct watchdog_device *wdd,
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unsigned int new_time)
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{
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wdd->timeout = new_time;
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return cdns_wdt_start(wdd);
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}
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/**
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* cdns_wdt_irq_handler - Notifies of watchdog timeout.
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*
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* @irq: interrupt number
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* @dev_id: pointer to a platform device structure
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* Return: IRQ_HANDLED
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*
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* The handler is invoked when the watchdog times out and a
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* reset on timeout has not been enabled.
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*/
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static irqreturn_t cdns_wdt_irq_handler(int irq, void *dev_id)
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{
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struct platform_device *pdev = dev_id;
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dev_info(&pdev->dev,
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"Watchdog timed out. Internal reset not enabled\n");
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return IRQ_HANDLED;
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}
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/*
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* Info structure used to indicate the features supported by the device
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* to the upper layers. This is defined in watchdog.h header file.
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*/
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static const struct watchdog_info cdns_wdt_info = {
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.identity = "cdns_wdt watchdog",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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};
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/* Watchdog Core Ops */
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static const struct watchdog_ops cdns_wdt_ops = {
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.owner = THIS_MODULE,
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.start = cdns_wdt_start,
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.stop = cdns_wdt_stop,
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.ping = cdns_wdt_reload,
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.set_timeout = cdns_wdt_settimeout,
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};
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static void cdns_clk_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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/************************Platform Operations*****************************/
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/**
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* cdns_wdt_probe - Probe call for the device.
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*
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* @pdev: handle to the platform device structure.
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* Return: 0 on success, negative error otherwise.
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*
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* It does all the memory allocation and registration for the device.
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*/
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static int cdns_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int ret, irq;
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unsigned long clock_f;
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struct cdns_wdt *wdt;
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struct watchdog_device *cdns_wdt_device;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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cdns_wdt_device = &wdt->cdns_wdt_device;
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cdns_wdt_device->info = &cdns_wdt_info;
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cdns_wdt_device->ops = &cdns_wdt_ops;
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cdns_wdt_device->timeout = CDNS_WDT_DEFAULT_TIMEOUT;
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cdns_wdt_device->min_timeout = CDNS_WDT_MIN_TIMEOUT;
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cdns_wdt_device->max_timeout = CDNS_WDT_MAX_TIMEOUT;
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wdt->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(wdt->regs))
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return PTR_ERR(wdt->regs);
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/* Register the interrupt */
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wdt->rst = of_property_read_bool(dev->of_node, "reset-on-timeout");
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irq = platform_get_irq(pdev, 0);
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if (!wdt->rst && irq >= 0) {
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ret = devm_request_irq(dev, irq, cdns_wdt_irq_handler, 0,
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pdev->name, pdev);
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if (ret) {
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dev_err(dev,
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"cannot register interrupt handler err=%d\n",
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ret);
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return ret;
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}
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}
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/* Initialize the members of cdns_wdt structure */
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cdns_wdt_device->parent = dev;
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watchdog_init_timeout(cdns_wdt_device, wdt_timeout, dev);
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watchdog_set_nowayout(cdns_wdt_device, nowayout);
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watchdog_stop_on_reboot(cdns_wdt_device);
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watchdog_set_drvdata(cdns_wdt_device, wdt);
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wdt->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(wdt->clk)) {
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ret = PTR_ERR(wdt->clk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "input clock not found\n");
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return ret;
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}
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ret = clk_prepare_enable(wdt->clk);
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if (ret) {
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dev_err(dev, "unable to enable clock\n");
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return ret;
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}
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ret = devm_add_action_or_reset(dev, cdns_clk_disable_unprepare,
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wdt->clk);
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if (ret)
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return ret;
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clock_f = clk_get_rate(wdt->clk);
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if (clock_f <= CDNS_WDT_CLK_75MHZ) {
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wdt->prescaler = CDNS_WDT_PRESCALE_512;
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wdt->ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;
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} else {
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wdt->prescaler = CDNS_WDT_PRESCALE_4096;
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wdt->ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;
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}
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spin_lock_init(&wdt->io_lock);
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watchdog_stop_on_reboot(cdns_wdt_device);
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watchdog_stop_on_unregister(cdns_wdt_device);
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ret = devm_watchdog_register_device(dev, cdns_wdt_device);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, wdt);
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dev_info(dev, "Xilinx Watchdog Timer at %p with timeout %ds%s\n",
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wdt->regs, cdns_wdt_device->timeout,
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nowayout ? ", nowayout" : "");
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return 0;
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}
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/**
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* cdns_wdt_suspend - Stop the device.
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*
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* @dev: handle to the device structure.
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* Return: 0 always.
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*/
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static int __maybe_unused cdns_wdt_suspend(struct device *dev)
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{
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struct cdns_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->cdns_wdt_device)) {
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cdns_wdt_stop(&wdt->cdns_wdt_device);
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clk_disable_unprepare(wdt->clk);
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}
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return 0;
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}
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/**
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* cdns_wdt_resume - Resume the device.
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*
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* @dev: handle to the device structure.
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* Return: 0 on success, errno otherwise.
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*/
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static int __maybe_unused cdns_wdt_resume(struct device *dev)
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{
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int ret;
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struct cdns_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->cdns_wdt_device)) {
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ret = clk_prepare_enable(wdt->clk);
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if (ret) {
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dev_err(dev, "unable to enable clock\n");
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return ret;
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}
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cdns_wdt_start(&wdt->cdns_wdt_device);
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}
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(cdns_wdt_pm_ops, cdns_wdt_suspend, cdns_wdt_resume);
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static const struct of_device_id cdns_wdt_of_match[] = {
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{ .compatible = "cdns,wdt-r1p2", },
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{ /* end of table */ }
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};
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MODULE_DEVICE_TABLE(of, cdns_wdt_of_match);
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/* Driver Structure */
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static struct platform_driver cdns_wdt_driver = {
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.probe = cdns_wdt_probe,
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.driver = {
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.name = "cdns-wdt",
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.of_match_table = cdns_wdt_of_match,
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.pm = &cdns_wdt_pm_ops,
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},
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};
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module_platform_driver(cdns_wdt_driver);
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MODULE_AUTHOR("Xilinx, Inc.");
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MODULE_DESCRIPTION("Watchdog driver for Cadence WDT");
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MODULE_LICENSE("GPL");
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