219 lines
5.3 KiB
Plaintext
219 lines
5.3 KiB
Plaintext
/*
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* Copyright 2012 ST-Ericsson AB
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ste-dbx5x0.dtsi"
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#include "ste-href-ab8500.dtsi"
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#include "ste-href.dtsi"
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/ {
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model = "ST-Ericsson HREF (v60+) platform with Device Tree";
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compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
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soc {
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// External Micro SD slot
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sdi0_per1@80126000 {
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cd-gpios = <&gpio2 31 0x4>; // 95
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};
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vmmci: regulator-gpio {
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gpios = <&gpio0 5 0x4>;
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enable-gpio = <&gpio5 9 0x4>;
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};
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pinctrl {
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/*
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* Set this up using hogs, as time goes by and as seems fit, these
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* can be moved over to being controlled by respective device.
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&ipgpio_hrefv60_mode>,
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<&etm_hrefv60_mode>,
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<&nahj_hrefv60_mode>,
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<&nfc_hrefv60_mode>,
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<&force_hrefv60_mode>,
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<&dipro_hrefv60_mode>,
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<&vaudio_hf_hrefv60_mode>,
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<&gbf_hrefv60_mode>,
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<&hdtv_hrefv60_mode>,
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<&touch_hrefv60_mode>;
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sdi0 {
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/* SD card detect GPIO pin, extend default state */
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sdi0_default_mode: sdi0_default {
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default_hrefv60_cfg1 {
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pins = "GPIO95_E8";
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ste,config = <&gpio_in_pu>;
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};
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};
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};
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ipgpio {
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/*
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* XENON Flashgun on image processor GPIO (controlled from image
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* processor firmware), mux in these image processor GPIO lines 0
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* (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
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* LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
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* from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
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*/
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ipgpio_hrefv60_mode: ipgpio_hrefv60 {
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hrefv60_mux {
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function = "ipgpio";
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groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
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};
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hrefv60_cfg1 {
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pins = "GPIO6_AF6", "GPIO7_AG5";
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ste,config = <&in_pu>;
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};
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hrefv60_cfg2 {
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pins = "GPIO21_AB3";
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ste,config = <&gpio_out_lo>;
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};
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hrefv60_cfg3 {
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pins = "GPIO64_F3";
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ste,config = <&out_lo>;
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};
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};
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};
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etm {
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/*
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* Drive D19-D23 for the ETM PTM trace interface low,
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* (presumably pins are unconnected therefore grounded here,
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* the "other alt C1" setting enables these pins)
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*/
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etm_hrefv60_mode: etm_hrefv60 {
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hrefv60_cfg1 {
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pins =
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"GPIO70_G5",
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"GPIO71_G4",
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"GPIO72_H4",
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"GPIO73_H3",
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"GPIO74_J3";
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ste,config = <&gpio_out_lo>;
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};
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};
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};
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nahj {
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nahj_hrefv60_mode: nahj_hrefv60 {
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/* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
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hrefv60_cfg1 {
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pins = "GPIO76_J2";
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ste,config = <&gpio_out_lo>;
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};
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hrefv60_cfg2 {
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pins = "GPIO216_AG12";
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ste,config = <&gpio_out_hi>;
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};
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};
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};
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nfc {
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nfc_hrefv60_mode: nfc_hrefv60 {
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/* NFC ENA and RESET to low, pulldown IRQ line */
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hrefv60_cfg1 {
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pins =
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"GPIO77_H1", /* NFC_ENA */
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"GPIO142_C11"; /* NFC_RESET */
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ste,config = <&gpio_out_lo>;
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};
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hrefv60_cfg2 {
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pins = "GPIO144_B13"; /* NFC_IRQ */
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ste,config = <&gpio_in_pd>;
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};
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};
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};
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force {
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force_hrefv60_mode: force_hrefv60 {
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hrefv60_cfg1 {
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pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
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ste,config = <&gpio_in_pu>;
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};
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hrefv60_cfg2 {
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pins =
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"GPIO92_D6", /* FORCE_SENSING_RST */
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"GPIO97_D9"; /* FORCE_SENSING_WU */
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ste,config = <&gpio_out_lo>;
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};
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};
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};
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dipro {
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dipro_hrefv60_mode: dipro_hrefv60 {
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hrefv60_cfg1 {
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pins = "GPIO139_C9"; /* DIPRO_INT */
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ste,config = <&gpio_in_pu>;
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};
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};
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};
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vaudio_hf {
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vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
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/* Audio Amplifier HF enable GPIO */
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hrefv60_cfg1 {
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pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
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ste,config = <&gpio_out_hi>;
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};
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};
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};
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gbf {
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gbf_hrefv60_mode: gbf_hrefv60 {
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/*
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* GBF (GPS, Bluetooth, FM-radio) interface,
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* pull low to reset state
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*/
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hrefv60_cfg1 {
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pins = "GPIO171_D23"; /* GBF_ENA_RESET */
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ste,config = <&gpio_out_lo>;
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};
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};
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};
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hdtv {
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hdtv_hrefv60_mode: hdtv_hrefv60 {
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/* MSP : HDTV INTERFACE GPIO line */
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hrefv60_cfg1 {
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pins = "GPIO192_AJ27";
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ste,config = <&gpio_in_pd>;
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};
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};
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};
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touch {
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touch_hrefv60_mode: touch_hrefv60 {
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/*
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* Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
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* GPIO 67 for interrupts. Pull-up the IRQ line and drive both
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* reset signals low.
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*/
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hrefv60_cfg1 {
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pins = "GPIO143_D12", "GPIO146_D13";
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ste,config = <&gpio_out_lo>;
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};
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hrefv60_cfg2 {
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pins = "GPIO67_G2";
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ste,config = <&gpio_in_pu>;
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};
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};
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};
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mcde {
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lcd_hrefv60_mode: lcd_hrefv60 {
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/*
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* Display Interface 1 uses GPIO 65 for RST (reset).
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* Display Interface 2 uses GPIO 66 for RST (reset).
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* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
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*/
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hrefv60_cfg1 {
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pins ="GPIO65_F1";
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ste,config = <&gpio_out_hi>;
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};
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hrefv60_cfg2 {
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pins ="GPIO66_G3";
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ste,config = <&gpio_out_lo>;
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};
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};
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};
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};
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};
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};
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