238 lines
6.2 KiB
C
238 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MDIO bus driver for the Xilinx Axi Ethernet device
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*
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* Copyright (c) 2009 Secret Lab Technologies, Ltd.
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* Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2010 - 2011 PetaLogix
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* Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
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*/
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/jiffies.h>
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#include "xilinx_axienet.h"
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#define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */
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#define DEFAULT_CLOCK_DIVISOR XAE_MDIO_DIV_DFT
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/* Wait till MDIO interface is ready to accept a new transaction.*/
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int axienet_mdio_wait_until_ready(struct axienet_local *lp)
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{
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unsigned long end = jiffies + 2;
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while (!(axienet_ior(lp, XAE_MDIO_MCR_OFFSET) &
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XAE_MDIO_MCR_READY_MASK)) {
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if (time_before_eq(end, jiffies)) {
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WARN_ON(1);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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return 0;
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}
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/**
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* axienet_mdio_read - MDIO interface read function
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* @bus: Pointer to mii bus structure
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* @phy_id: Address of the PHY device
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* @reg: PHY register to read
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*
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* Return: The register contents on success, -ETIMEDOUT on a timeout
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*
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* Reads the contents of the requested register from the requested PHY
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* address by first writing the details into MCR register. After a while
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* the register MRD is read to obtain the PHY register content.
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*/
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static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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{
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u32 rc;
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int ret;
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struct axienet_local *lp = bus->priv;
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ret = axienet_mdio_wait_until_ready(lp);
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if (ret < 0)
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return ret;
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axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
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(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
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XAE_MDIO_MCR_PHYAD_MASK) |
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((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
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XAE_MDIO_MCR_REGAD_MASK) |
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XAE_MDIO_MCR_INITIATE_MASK |
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XAE_MDIO_MCR_OP_READ_MASK));
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ret = axienet_mdio_wait_until_ready(lp);
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if (ret < 0)
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return ret;
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rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
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dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
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phy_id, reg, rc);
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return rc;
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}
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/**
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* axienet_mdio_write - MDIO interface write function
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* @bus: Pointer to mii bus structure
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* @phy_id: Address of the PHY device
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* @reg: PHY register to write to
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* @val: Value to be written into the register
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*
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* Return: 0 on success, -ETIMEDOUT on a timeout
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*
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* Writes the value to the requested register by first writing the value
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* into MWD register. The the MCR register is then appropriately setup
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* to finish the write operation.
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*/
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static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
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u16 val)
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{
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int ret;
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struct axienet_local *lp = bus->priv;
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dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
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phy_id, reg, val);
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ret = axienet_mdio_wait_until_ready(lp);
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if (ret < 0)
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return ret;
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axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
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axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
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(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
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XAE_MDIO_MCR_PHYAD_MASK) |
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((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
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XAE_MDIO_MCR_REGAD_MASK) |
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XAE_MDIO_MCR_INITIATE_MASK |
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XAE_MDIO_MCR_OP_WRITE_MASK));
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ret = axienet_mdio_wait_until_ready(lp);
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if (ret < 0)
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return ret;
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return 0;
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}
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/**
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* axienet_mdio_setup - MDIO setup function
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* @lp: Pointer to axienet local data structure.
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* @np: Pointer to device node
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*
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* Return: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
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* mdiobus_alloc (to allocate memory for mii bus structure) fails.
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*
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* Sets up the MDIO interface by initializing the MDIO clock and enabling the
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* MDIO interface in hardware. Register the MDIO interface.
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**/
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int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
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{
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int ret;
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u32 clk_div, host_clock;
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struct mii_bus *bus;
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struct resource res;
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struct device_node *np1;
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/* clk_div can be calculated by deriving it from the equation:
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* fMDIO = fHOST / ((1 + clk_div) * 2)
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*
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* Where fMDIO <= 2500000, so we get:
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* fHOST / ((1 + clk_div) * 2) <= 2500000
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*
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* Then we get:
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* 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
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*
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* Then we get:
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* 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
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*
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* Then we get:
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* 1 / (1 + clk_div) <= (5000000 / fHOST)
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*
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* So:
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* (1 + clk_div) >= (fHOST / 5000000)
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*
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* And finally:
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* clk_div >= (fHOST / 5000000) - 1
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*
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* fHOST can be read from the flattened device tree as property
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* "clock-frequency" from the CPU
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*/
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np1 = of_find_node_by_name(NULL, "cpu");
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if (!np1) {
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netdev_warn(lp->ndev, "Could not find CPU device node.\n");
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netdev_warn(lp->ndev,
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"Setting MDIO clock divisor to default %d\n",
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DEFAULT_CLOCK_DIVISOR);
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clk_div = DEFAULT_CLOCK_DIVISOR;
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goto issue;
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}
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if (of_property_read_u32(np1, "clock-frequency", &host_clock)) {
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netdev_warn(lp->ndev, "clock-frequency property not found.\n");
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netdev_warn(lp->ndev,
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"Setting MDIO clock divisor to default %d\n",
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DEFAULT_CLOCK_DIVISOR);
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clk_div = DEFAULT_CLOCK_DIVISOR;
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of_node_put(np1);
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goto issue;
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}
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clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
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/* If there is any remainder from the division of
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* fHOST / (MAX_MDIO_FREQ * 2), then we need to add
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* 1 to the clock divisor or we will surely be above 2.5 MHz
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*/
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if (host_clock % (MAX_MDIO_FREQ * 2))
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clk_div++;
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netdev_dbg(lp->ndev,
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"Setting MDIO clock divisor to %u/%u Hz host clock.\n",
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clk_div, host_clock);
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of_node_put(np1);
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issue:
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axienet_iow(lp, XAE_MDIO_MC_OFFSET,
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(((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK));
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ret = axienet_mdio_wait_until_ready(lp);
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if (ret < 0)
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return ret;
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bus = mdiobus_alloc();
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if (!bus)
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return -ENOMEM;
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np1 = of_get_parent(lp->phy_node);
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of_address_to_resource(np1, 0, &res);
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snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
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(unsigned long long) res.start);
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bus->priv = lp;
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bus->name = "Xilinx Axi Ethernet MDIO";
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bus->read = axienet_mdio_read;
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bus->write = axienet_mdio_write;
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bus->parent = lp->dev;
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lp->mii_bus = bus;
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ret = of_mdiobus_register(bus, np1);
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if (ret) {
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mdiobus_free(bus);
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return ret;
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}
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return 0;
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}
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/**
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* axienet_mdio_teardown - MDIO remove function
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* @lp: Pointer to axienet local data structure.
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*
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* Unregisters the MDIO and frees any associate memory for mii bus.
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*/
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void axienet_mdio_teardown(struct axienet_local *lp)
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{
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mdiobus_unregister(lp->mii_bus);
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mdiobus_free(lp->mii_bus);
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lp->mii_bus = NULL;
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}
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