633 lines
17 KiB
C
633 lines
17 KiB
C
/*
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* tegra30_ahub.c - Tegra30 AHUB driver
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*
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* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <mach/clk.h>
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#include <mach/dma.h>
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#include <sound/soc.h>
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#include "tegra30_ahub.h"
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#define DRV_NAME "tegra30-ahub"
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static struct tegra30_ahub *ahub;
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static inline void tegra30_apbif_write(u32 reg, u32 val)
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{
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regmap_write(ahub->regmap_apbif, reg, val);
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}
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static inline u32 tegra30_apbif_read(u32 reg)
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{
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u32 val;
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regmap_read(ahub->regmap_apbif, reg, &val);
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return val;
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}
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static inline void tegra30_audio_write(u32 reg, u32 val)
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{
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regmap_write(ahub->regmap_ahub, reg, val);
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}
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static int tegra30_ahub_runtime_suspend(struct device *dev)
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{
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regcache_cache_only(ahub->regmap_apbif, true);
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regcache_cache_only(ahub->regmap_ahub, true);
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clk_disable_unprepare(ahub->clk_apbif);
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clk_disable_unprepare(ahub->clk_d_audio);
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return 0;
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}
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/*
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* clk_apbif isn't required for an I2S<->I2S configuration where no PCM data
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* is read from or sent to memory. However, that's not something the rest of
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* the driver supports right now, so we'll just treat the two clocks as one
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* for now.
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*
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* These functions should not be a plain ref-count. Instead, each active stream
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* contributes some requirement to the minimum clock rate, so starting or
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* stopping streams should dynamically adjust the clock as required. However,
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* this is not yet implemented.
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*/
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static int tegra30_ahub_runtime_resume(struct device *dev)
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{
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int ret;
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ret = clk_prepare_enable(ahub->clk_d_audio);
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if (ret) {
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dev_err(dev, "clk_enable d_audio failed: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(ahub->clk_apbif);
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if (ret) {
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dev_err(dev, "clk_enable apbif failed: %d\n", ret);
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clk_disable(ahub->clk_d_audio);
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return ret;
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}
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regcache_cache_only(ahub->regmap_apbif, false);
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regcache_cache_only(ahub->regmap_ahub, false);
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return 0;
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}
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int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
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unsigned long *fiforeg,
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unsigned long *reqsel)
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{
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int channel;
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u32 reg, val;
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channel = find_first_zero_bit(ahub->rx_usage,
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TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
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if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
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return -EBUSY;
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__set_bit(channel, ahub->rx_usage);
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*rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
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*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
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(channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
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*reqsel = ahub->dma_sel + channel;
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK |
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TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK);
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val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) |
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TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN |
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TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16;
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tegra30_apbif_write(reg, val);
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reg = TEGRA30_AHUB_CIF_RX_CTRL +
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(channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
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val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
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(1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
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(1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
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TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
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TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 |
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TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
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tegra30_apbif_write(reg, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
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int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
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{
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg, val;
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
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tegra30_apbif_write(reg, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
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int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
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{
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg, val;
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
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tegra30_apbif_write(reg, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
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int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
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{
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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__clear_bit(channel, ahub->rx_usage);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
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int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
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unsigned long *fiforeg,
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unsigned long *reqsel)
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{
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int channel;
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u32 reg, val;
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channel = find_first_zero_bit(ahub->tx_usage,
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TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
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if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
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return -EBUSY;
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__set_bit(channel, ahub->tx_usage);
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*txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
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*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
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(channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
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*reqsel = ahub->dma_sel + channel;
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK |
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TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK);
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val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) |
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TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN |
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TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16;
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tegra30_apbif_write(reg, val);
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reg = TEGRA30_AHUB_CIF_TX_CTRL +
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(channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
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val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
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(1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
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(1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
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TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
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TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 |
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TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
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tegra30_apbif_write(reg, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
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int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
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{
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
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int reg, val;
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
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tegra30_apbif_write(reg, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
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int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
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{
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
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int reg, val;
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
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tegra30_apbif_write(reg, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
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int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif)
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{
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
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__clear_bit(channel, ahub->tx_usage);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo);
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int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
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enum tegra30_ahub_txcif txcif)
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{
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg;
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reg = TEGRA30_AHUB_AUDIO_RX +
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(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
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tegra30_audio_write(reg, 1 << txcif);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
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int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
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{
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg;
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reg = TEGRA30_AHUB_AUDIO_RX +
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(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
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tegra30_audio_write(reg, 0);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
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static const char * const configlink_clocks[] __devinitconst = {
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"i2s0",
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"i2s1",
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"i2s2",
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"i2s3",
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"i2s4",
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"dam0",
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"dam1",
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"dam2",
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"spdif_in",
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};
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struct of_dev_auxdata ahub_auxdata[] __devinitdata = {
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OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080300, "tegra30-i2s.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080400, "tegra30-i2s.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080500, "tegra30-i2s.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080600, "tegra30-i2s.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080700, "tegra30-i2s.4", NULL),
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{}
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};
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#define LAST_REG(name) \
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(TEGRA30_AHUB_##name + \
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(TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4)
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#define REG_IN_ARRAY(reg, name) \
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((reg >= TEGRA30_AHUB_##name) && \
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(reg <= LAST_REG(name) && \
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(!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
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static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA30_AHUB_CONFIG_LINK_CTRL:
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case TEGRA30_AHUB_MISC_CTRL:
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case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
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case TEGRA30_AHUB_I2S_LIVE_STATUS:
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case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
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case TEGRA30_AHUB_I2S_INT_MASK:
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case TEGRA30_AHUB_DAM_INT_MASK:
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case TEGRA30_AHUB_SPDIF_INT_MASK:
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case TEGRA30_AHUB_APBIF_INT_MASK:
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case TEGRA30_AHUB_I2S_INT_STATUS:
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case TEGRA30_AHUB_DAM_INT_STATUS:
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case TEGRA30_AHUB_SPDIF_INT_STATUS:
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case TEGRA30_AHUB_APBIF_INT_STATUS:
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case TEGRA30_AHUB_I2S_INT_SOURCE:
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case TEGRA30_AHUB_DAM_INT_SOURCE:
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case TEGRA30_AHUB_SPDIF_INT_SOURCE:
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case TEGRA30_AHUB_APBIF_INT_SOURCE:
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case TEGRA30_AHUB_I2S_INT_SET:
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case TEGRA30_AHUB_DAM_INT_SET:
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case TEGRA30_AHUB_SPDIF_INT_SET:
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case TEGRA30_AHUB_APBIF_INT_SET:
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return true;
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default:
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break;
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};
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if (REG_IN_ARRAY(reg, CHANNEL_CTRL) ||
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REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
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REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
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REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
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REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
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REG_IN_ARRAY(reg, CIF_TX_CTRL) ||
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REG_IN_ARRAY(reg, CIF_RX_CTRL) ||
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REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
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return true;
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return false;
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}
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static bool tegra30_ahub_apbif_volatile_reg(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case TEGRA30_AHUB_CONFIG_LINK_CTRL:
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case TEGRA30_AHUB_MISC_CTRL:
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case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
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case TEGRA30_AHUB_I2S_LIVE_STATUS:
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case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
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case TEGRA30_AHUB_I2S_INT_STATUS:
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case TEGRA30_AHUB_DAM_INT_STATUS:
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case TEGRA30_AHUB_SPDIF_INT_STATUS:
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case TEGRA30_AHUB_APBIF_INT_STATUS:
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case TEGRA30_AHUB_I2S_INT_SET:
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case TEGRA30_AHUB_DAM_INT_SET:
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case TEGRA30_AHUB_SPDIF_INT_SET:
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case TEGRA30_AHUB_APBIF_INT_SET:
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return true;
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default:
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break;
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};
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if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
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REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
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REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
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REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
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REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
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return true;
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return false;
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}
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static bool tegra30_ahub_apbif_precious_reg(struct device *dev,
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unsigned int reg)
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{
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if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
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REG_IN_ARRAY(reg, CHANNEL_RXFIFO))
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return true;
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return false;
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}
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static const struct regmap_config tegra30_ahub_apbif_regmap_config = {
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.name = "apbif",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = TEGRA30_AHUB_APBIF_INT_SET,
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.writeable_reg = tegra30_ahub_apbif_wr_rd_reg,
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.readable_reg = tegra30_ahub_apbif_wr_rd_reg,
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.volatile_reg = tegra30_ahub_apbif_volatile_reg,
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.precious_reg = tegra30_ahub_apbif_precious_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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if (REG_IN_ARRAY(reg, AUDIO_RX))
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return true;
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return false;
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}
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static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
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.name = "ahub",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = LAST_REG(AUDIO_RX),
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.writeable_reg = tegra30_ahub_ahub_wr_rd_reg,
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.readable_reg = tegra30_ahub_ahub_wr_rd_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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static int __devinit tegra30_ahub_probe(struct platform_device *pdev)
|
|
{
|
|
struct clk *clk;
|
|
int i;
|
|
struct resource *res0, *res1, *region;
|
|
u32 of_dma[2];
|
|
void __iomem *regs_apbif, *regs_ahub;
|
|
int ret = 0;
|
|
|
|
if (ahub)
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* The AHUB hosts a register bus: the "configlink". For this to
|
|
* operate correctly, all devices on this bus must be out of reset.
|
|
* Ensure that here.
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
|
|
clk = clk_get_sys(NULL, configlink_clocks[i]);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(&pdev->dev, "Can't get clock %s\n",
|
|
configlink_clocks[i]);
|
|
ret = PTR_ERR(clk);
|
|
goto err;
|
|
}
|
|
tegra_periph_reset_deassert(clk);
|
|
clk_put(clk);
|
|
}
|
|
|
|
ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
|
|
GFP_KERNEL);
|
|
if (!ahub) {
|
|
dev_err(&pdev->dev, "Can't allocate tegra30_ahub\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
dev_set_drvdata(&pdev->dev, ahub);
|
|
|
|
ahub->dev = &pdev->dev;
|
|
|
|
ahub->clk_d_audio = clk_get(&pdev->dev, "d_audio");
|
|
if (IS_ERR(ahub->clk_d_audio)) {
|
|
dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n");
|
|
ret = PTR_ERR(ahub->clk_d_audio);
|
|
goto err;
|
|
}
|
|
|
|
ahub->clk_apbif = clk_get(&pdev->dev, "apbif");
|
|
if (IS_ERR(ahub->clk_apbif)) {
|
|
dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n");
|
|
ret = PTR_ERR(ahub->clk_apbif);
|
|
goto err_clk_put_d_audio;
|
|
}
|
|
|
|
if (of_property_read_u32_array(pdev->dev.of_node,
|
|
"nvidia,dma-request-selector",
|
|
of_dma, 2) < 0) {
|
|
dev_err(&pdev->dev,
|
|
"Missing property nvidia,dma-request-selector\n");
|
|
ret = -ENODEV;
|
|
goto err_clk_put_d_audio;
|
|
}
|
|
ahub->dma_sel = of_dma[1];
|
|
|
|
res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res0) {
|
|
dev_err(&pdev->dev, "No apbif memory resource\n");
|
|
ret = -ENODEV;
|
|
goto err_clk_put_apbif;
|
|
}
|
|
|
|
region = devm_request_mem_region(&pdev->dev, res0->start,
|
|
resource_size(res0), DRV_NAME);
|
|
if (!region) {
|
|
dev_err(&pdev->dev, "request region apbif failed\n");
|
|
ret = -EBUSY;
|
|
goto err_clk_put_apbif;
|
|
}
|
|
ahub->apbif_addr = res0->start;
|
|
|
|
regs_apbif = devm_ioremap(&pdev->dev, res0->start,
|
|
resource_size(res0));
|
|
if (!regs_apbif) {
|
|
dev_err(&pdev->dev, "ioremap apbif failed\n");
|
|
ret = -ENOMEM;
|
|
goto err_clk_put_apbif;
|
|
}
|
|
|
|
ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif,
|
|
&tegra30_ahub_apbif_regmap_config);
|
|
if (IS_ERR(ahub->regmap_apbif)) {
|
|
dev_err(&pdev->dev, "apbif regmap init failed\n");
|
|
ret = PTR_ERR(ahub->regmap_apbif);
|
|
goto err_clk_put_apbif;
|
|
}
|
|
regcache_cache_only(ahub->regmap_apbif, true);
|
|
|
|
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (!res1) {
|
|
dev_err(&pdev->dev, "No ahub memory resource\n");
|
|
ret = -ENODEV;
|
|
goto err_clk_put_apbif;
|
|
}
|
|
|
|
region = devm_request_mem_region(&pdev->dev, res1->start,
|
|
resource_size(res1), DRV_NAME);
|
|
if (!region) {
|
|
dev_err(&pdev->dev, "request region ahub failed\n");
|
|
ret = -EBUSY;
|
|
goto err_clk_put_apbif;
|
|
}
|
|
|
|
regs_ahub = devm_ioremap(&pdev->dev, res1->start,
|
|
resource_size(res1));
|
|
if (!regs_ahub) {
|
|
dev_err(&pdev->dev, "ioremap ahub failed\n");
|
|
ret = -ENOMEM;
|
|
goto err_clk_put_apbif;
|
|
}
|
|
|
|
ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub,
|
|
&tegra30_ahub_ahub_regmap_config);
|
|
if (IS_ERR(ahub->regmap_ahub)) {
|
|
dev_err(&pdev->dev, "ahub regmap init failed\n");
|
|
ret = PTR_ERR(ahub->regmap_ahub);
|
|
goto err_clk_put_apbif;
|
|
}
|
|
regcache_cache_only(ahub->regmap_ahub, true);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
ret = tegra30_ahub_runtime_resume(&pdev->dev);
|
|
if (ret)
|
|
goto err_pm_disable;
|
|
}
|
|
|
|
of_platform_populate(pdev->dev.of_node, NULL, ahub_auxdata,
|
|
&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err_clk_put_apbif:
|
|
clk_put(ahub->clk_apbif);
|
|
err_clk_put_d_audio:
|
|
clk_put(ahub->clk_d_audio);
|
|
ahub = 0;
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit tegra30_ahub_remove(struct platform_device *pdev)
|
|
{
|
|
if (!ahub)
|
|
return -ENODEV;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra30_ahub_runtime_suspend(&pdev->dev);
|
|
|
|
clk_put(ahub->clk_apbif);
|
|
clk_put(ahub->clk_d_audio);
|
|
|
|
ahub = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id tegra30_ahub_of_match[] __devinitconst = {
|
|
{ .compatible = "nvidia,tegra30-ahub", },
|
|
{},
|
|
};
|
|
|
|
static const struct dev_pm_ops tegra30_ahub_pm_ops __devinitconst = {
|
|
SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend,
|
|
tegra30_ahub_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver tegra30_ahub_driver = {
|
|
.probe = tegra30_ahub_probe,
|
|
.remove = __devexit_p(tegra30_ahub_remove),
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra30_ahub_of_match,
|
|
.pm = &tegra30_ahub_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(tegra30_ahub_driver);
|
|
|
|
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra30 AHUB driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match);
|