1241 lines
29 KiB
Plaintext
1241 lines
29 KiB
Plaintext
/*
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* sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
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*
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* Copyright (C) 2014 Atmel,
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* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Atmel SAMA5D4 family SoC";
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compatible = "atmel,sama5d4";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &usart3;
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serial1 = &usart4;
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serial2 = &usart2;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio4 = &pioE;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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i2c2 = &i2c2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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reg = <0x20000000 0x20000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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adc_op_clk: adc_op_clk{
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb0: gadget@00400000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,at91sam9rl-udc";
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reg = <0x00400000 0x100000
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0xfc02c000 0x4000>;
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interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udphs_clk>, <&utmi>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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ep0 {
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reg = <0>;
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atmel,fifo-size = <64>;
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atmel,nb-banks = <1>;
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};
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ep1 {
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reg = <1>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep2 {
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reg = <2>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep3 {
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reg = <3>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep4 {
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reg = <4>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep5 {
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reg = <5>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep6 {
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reg = <6>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep7 {
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reg = <7>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep8 {
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reg = <8>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep9 {
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reg = <9>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep10 {
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reg = <10>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep11 {
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reg = <11>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep12 {
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reg = <12>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep13 {
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reg = <13>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep14 {
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reg = <14>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep15 {
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reg = <15>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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};
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usb1: ohci@00500000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00500000 0x100000>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
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<&uhpck>;
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clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@00600000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00600000 0x100000>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
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clock-names = "usb_clk", "ehci_clk", "uhpck";
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status = "disabled";
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};
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L2: cache-controller@00a00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a00000 0x1000>;
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interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
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cache-unified;
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cache-level = <2>;
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};
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nand0: nand@80000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = < 0x80000000 0x08000000 /* EBI CS3 */
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0xfc05c070 0x00000490 /* SMC PMECC regs */
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0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
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>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
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atmel,nand-addr-offset = <21>;
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atmel,nand-cmd-offset = <22>;
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atmel,nand-has-dma;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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status = "disabled";
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nfc@90000000 {
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compatible = "atmel,sama5d3-nfc";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <
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0x90000000 0x10000000 /* NFC Command Registers */
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0xfc05c000 0x00000070 /* NFC HSMC regs */
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0x00100000 0x00100000 /* NFC SRAM banks */
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>;
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clocks = <&hsmc_clk>;
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atmel,write-by-sram;
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};
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ramc0: ramc@f0010000 {
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compatible = "atmel,sama5d3-ddramc";
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reg = <0xf0010000 0x200>;
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clocks = <&ddrck>, <&mpddr_clk>;
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clock-names = "ddrck", "mpddr";
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};
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pmc: pmc@f0018000 {
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compatible = "atmel,sama5d3-pmc";
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reg = <0xf0018000 0x120>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCRCS>;
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clock-frequency = <12000000>;
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clock-accuracy = <100000000>;
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};
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCS>;
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clocks = <&main_xtal>;
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};
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCSELS>;
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clocks = <&main_rc_osc &main_osc>;
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};
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plla: pllack {
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKA>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <12000000 12000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKU>;
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clocks = <&main>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MCKRDY>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <125000000 177000000>;
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atmel,clk-divisors = <1 2 4 3>;
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};
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h32ck: h32mxck {
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#clock-cells = <0>;
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compatible = "atmel,sama5d4-clk-h32mx";
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clocks = <&mck>;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <AT91_PMC_PCKRDY(0)>;
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};
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prog1: prog1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <AT91_PMC_PCKRDY(1)>;
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};
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prog2: prog2 {
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#clock-cells = <0>;
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reg = <2>;
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interrupts = <AT91_PMC_PCKRDY(2)>;
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};
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};
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smd: smdclk {
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compatible = "atmel,at91sam9x5-clk-smd";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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lcdck: lcdck {
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#clock-cells = <0>;
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reg = <4>;
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clocks = <&smd>;
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};
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smdck: smdck {
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#clock-cells = <0>;
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reg = <4>;
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clocks = <&smd>;
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};
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uhpck: uhpck {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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pck2: pck2 {
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#clock-cells = <0>;
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reg = <10>;
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clocks = <&prog2>;
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};
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};
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periph32ck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&h32ck>;
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pioD_clk: pioD_clk {
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#clock-cells = <0>;
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reg = <5>;
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};
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usart0_clk: usart0_clk {
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#clock-cells = <0>;
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reg = <6>;
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};
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usart1_clk: usart1_clk {
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#clock-cells = <0>;
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reg = <7>;
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};
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icm_clk: icm_clk {
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#clock-cells = <0>;
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reg = <9>;
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};
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aes_clk: aes_clk {
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#clock-cells = <0>;
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reg = <12>;
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};
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tdes_clk: tdes_clk {
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#clock-cells = <0>;
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reg = <14>;
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};
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sha_clk: sha_clk {
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#clock-cells = <0>;
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reg = <15>;
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};
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matrix1_clk: matrix1_clk {
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#clock-cells = <0>;
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reg = <17>;
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};
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hsmc_clk: hsmc_clk {
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#clock-cells = <0>;
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reg = <22>;
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};
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pioA_clk: pioA_clk {
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#clock-cells = <0>;
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reg = <23>;
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};
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pioB_clk: pioB_clk {
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#clock-cells = <0>;
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reg = <24>;
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};
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pioC_clk: pioC_clk {
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#clock-cells = <0>;
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reg = <25>;
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};
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pioE_clk: pioE_clk {
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#clock-cells = <0>;
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reg = <26>;
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};
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|
|
uart0_clk: uart0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <27>;
|
|
};
|
|
|
|
uart1_clk: uart1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <28>;
|
|
};
|
|
|
|
usart2_clk: usart2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <29>;
|
|
};
|
|
|
|
usart3_clk: usart3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <30>;
|
|
};
|
|
|
|
usart4_clk: usart4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk {
|
|
reg = <32>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
twi1_clk: twi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <33>;
|
|
};
|
|
|
|
twi2_clk: twi2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <34>;
|
|
};
|
|
|
|
mci0_clk: mci0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
};
|
|
|
|
mci1_clk: mci1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <37>;
|
|
};
|
|
|
|
spi1_clk: spi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
};
|
|
|
|
spi2_clk: spi2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <39>;
|
|
};
|
|
|
|
tcb0_clk: tcb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <40>;
|
|
};
|
|
|
|
tcb1_clk: tcb1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <41>;
|
|
};
|
|
|
|
tcb2_clk: tcb2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <42>;
|
|
};
|
|
|
|
pwm_clk: pwm_clk {
|
|
#clock-cells = <0>;
|
|
reg = <43>;
|
|
};
|
|
|
|
adc_clk: adc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <44>;
|
|
};
|
|
|
|
dbgu_clk: dbgu_clk {
|
|
#clock-cells = <0>;
|
|
reg = <45>;
|
|
};
|
|
|
|
uhphs_clk: uhphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <46>;
|
|
};
|
|
|
|
udphs_clk: udphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <47>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <49>;
|
|
};
|
|
|
|
trng_clk: trng_clk {
|
|
#clock-cells = <0>;
|
|
reg = <53>;
|
|
};
|
|
|
|
macb0_clk: macb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
};
|
|
|
|
macb1_clk: macb1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
};
|
|
|
|
fuse_clk: fuse_clk {
|
|
#clock-cells = <0>;
|
|
reg = <57>;
|
|
};
|
|
|
|
securam_clk: securam_clk {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
};
|
|
|
|
smd_clk: smd_clk {
|
|
#clock-cells = <0>;
|
|
reg = <61>;
|
|
};
|
|
|
|
twi3_clk: twi3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <62>;
|
|
};
|
|
|
|
catb_clk: catb_clk {
|
|
#clock-cells = <0>;
|
|
reg = <63>;
|
|
};
|
|
};
|
|
|
|
periph64ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
|
|
dma0_clk: dma0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
};
|
|
|
|
cpkcc_clk: cpkcc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
aesb_clk: aesb_clk {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
};
|
|
|
|
mpddr_clk: mpddr_clk {
|
|
#clock-cells = <0>;
|
|
reg = <16>;
|
|
};
|
|
|
|
matrix0_clk: matrix0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
};
|
|
|
|
vdec_clk: vdec_clk {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
};
|
|
|
|
dma1_clk: dma1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <50>;
|
|
};
|
|
|
|
lcd_clk: lcd_clk {
|
|
#clock-cells = <0>;
|
|
reg = <51>;
|
|
};
|
|
|
|
isi_clk: isi_clk {
|
|
#clock-cells = <0>;
|
|
reg = <52>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mmc0: mmc@f8000000 {
|
|
compatible = "atmel,hsmci";
|
|
reg = <0xf8000000 0x600>;
|
|
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mci0_clk>;
|
|
clock-names = "mci_clk";
|
|
};
|
|
|
|
spi0: spi@f8010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi0>;
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8014000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8014000 0x4000>;
|
|
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@f801c000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf801c000 0x100>;
|
|
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb0_clk>;
|
|
clock-names = "t0_clk";
|
|
};
|
|
|
|
macb0: ethernet@f8020000 {
|
|
compatible = "atmel,sama5d4-gem";
|
|
reg = <0xf8020000 0x100>;
|
|
interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_macb0_rmii>;
|
|
clocks = <&macb0_clk>, <&macb0_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@f8024000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8024000 0x4000>;
|
|
interrupts = <34 4 6>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi2_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@fc000000 {
|
|
compatible = "atmel,hsmci";
|
|
reg = <0xfc000000 0x600>;
|
|
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mci1_clk>;
|
|
clock-names = "mci_clk";
|
|
};
|
|
|
|
usart2: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
|
|
clocks = <&usart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart3>;
|
|
clocks = <&usart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart4: serial@fc010000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc010000 0x100>;
|
|
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart4>;
|
|
clocks = <&usart4_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb1: timer@fc020000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xfc020000 0x100>;
|
|
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb1_clk>;
|
|
clock-names = "t0_clk";
|
|
};
|
|
|
|
adc0: adc@fc034000 {
|
|
compatible = "atmel,at91sam9x5-adc";
|
|
reg = <0xfc034000 0x100>;
|
|
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <
|
|
/* external trigger is conflict with USBA_VBUS */
|
|
&pinctrl_adc0_ad0
|
|
&pinctrl_adc0_ad1
|
|
&pinctrl_adc0_ad2
|
|
&pinctrl_adc0_ad3
|
|
&pinctrl_adc0_ad4
|
|
>;
|
|
clocks = <&adc_clk>,
|
|
<&adc_op_clk>;
|
|
clock-names = "adc_clk", "adc_op_clk";
|
|
atmel,adc-channels-used = <0x01f>;
|
|
atmel,adc-startup-time = <40>;
|
|
atmel,adc-use-external;
|
|
atmel,adc-vref = <3000>;
|
|
atmel,adc-res = <8 10>;
|
|
atmel,adc-sample-hold-time = <11>;
|
|
atmel,adc-res-names = "lowres", "highres";
|
|
atmel,adc-ts-pressure-threshold = <10000>;
|
|
status = "disabled";
|
|
|
|
trigger@0 {
|
|
trigger-name = "external-rising";
|
|
trigger-value = <0x1>;
|
|
trigger-external;
|
|
};
|
|
trigger@1 {
|
|
trigger-name = "external-falling";
|
|
trigger-value = <0x2>;
|
|
trigger-external;
|
|
};
|
|
trigger@2 {
|
|
trigger-name = "external-any";
|
|
trigger-value = <0x3>;
|
|
trigger-external;
|
|
};
|
|
trigger@3 {
|
|
trigger-name = "continuous";
|
|
trigger-value = <0x6>;
|
|
};
|
|
};
|
|
|
|
rstc@fc068600 {
|
|
compatible = "atmel,at91sam9g45-rstc";
|
|
reg = <0xfc068600 0x10>;
|
|
};
|
|
|
|
shdwc@fc068610 {
|
|
compatible = "atmel,at91sam9x5-shdwc";
|
|
reg = <0xfc068610 0x10>;
|
|
};
|
|
|
|
pit: timer@fc068630 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xfc068630 0xf>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
clocks = <&h32ck>;
|
|
};
|
|
|
|
watchdog@fc068640 {
|
|
compatible = "atmel,at91sam9260-wdt";
|
|
reg = <0xfc068640 0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sckc@fc068650 {
|
|
compatible = "atmel,at91sam9x5-sckc";
|
|
reg = <0xfc068650 0x4>;
|
|
|
|
slow_rc_osc: slow_rc_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-accuracy = <250000000>;
|
|
atmel,startup-time-usec = <75>;
|
|
};
|
|
|
|
slow_osc: slow_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_xtal>;
|
|
atmel,startup-time-usec = <1200000>;
|
|
};
|
|
|
|
clk32k: slowck {
|
|
compatible = "atmel,at91sam9x5-clk-slow";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_rc_osc &slow_osc>;
|
|
};
|
|
};
|
|
|
|
rtc@fc0686b0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xfc0686b0 0x30>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
};
|
|
|
|
dbgu: serial@fc069000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc069000 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dbgu>;
|
|
clocks = <&dbgu_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
pinctrl@fc06a000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
|
ranges = <0xfc06a000 0xfc06a000 0x4000>;
|
|
/* WARNING: revisit as pin spec has changed */
|
|
atmel,mux-mask = <
|
|
/* A B C */
|
|
0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
|
|
0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
|
|
0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
|
|
0x00000000 0x00000000 0x00000000 /* pioD */
|
|
0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
|
|
>;
|
|
|
|
pioA: gpio@fc06a000 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfc06a000 0x100>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioA_clk>;
|
|
};
|
|
|
|
pioB: gpio@fc06b000 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfc06b000 0x100>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioB_clk>;
|
|
};
|
|
|
|
pioC: gpio@fc06c000 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfc06c000 0x100>;
|
|
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioC_clk>;
|
|
};
|
|
|
|
pioE: gpio@fc06d000 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfc06d000 0x100>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioE_clk>;
|
|
};
|
|
|
|
/* pinctrl pin settings */
|
|
adc0 {
|
|
pinctrl_adc0_adtrg: adc0_adtrg {
|
|
atmel,pins =
|
|
<AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
|
|
};
|
|
pinctrl_adc0_ad0: adc0_ad0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_adc0_ad1: adc0_ad1 {
|
|
atmel,pins =
|
|
<AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_adc0_ad2: adc0_ad2 {
|
|
atmel,pins =
|
|
<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_adc0_ad3: adc0_ad3 {
|
|
atmel,pins =
|
|
<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_adc0_ad4: adc0_ad4 {
|
|
atmel,pins =
|
|
<AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
dbgu {
|
|
pinctrl_dbgu: dbgu-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
|
|
<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
pinctrl_i2c0: i2c0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
|
|
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
pinctrl_i2c2: i2c2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
|
|
AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
|
|
};
|
|
};
|
|
|
|
macb0 {
|
|
pinctrl_macb0_rmii: macb0_rmii-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
|
|
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
|
|
AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
|
|
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
|
|
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
|
|
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
|
|
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
|
|
AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
|
|
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
|
|
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
|
|
>;
|
|
};
|
|
};
|
|
|
|
mmc0 {
|
|
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
|
|
AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
|
|
AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
|
|
>;
|
|
};
|
|
pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
|
|
atmel,pins =
|
|
<AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
|
|
AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
|
|
AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
|
|
>;
|
|
};
|
|
};
|
|
|
|
mmc1 {
|
|
pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
|
|
AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
|
|
AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
|
|
>;
|
|
};
|
|
pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
|
|
atmel,pins =
|
|
<AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
|
|
AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
|
|
AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
|
|
>;
|
|
};
|
|
};
|
|
|
|
nand0 {
|
|
pinctrl_nand: nand-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
|
|
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
|
|
|
|
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
|
|
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
|
|
|
|
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
|
|
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
|
|
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
|
|
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
|
|
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
|
|
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
|
|
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
|
|
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
|
|
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
|
|
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
pinctrl_spi0: spi0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
|
|
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
|
|
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
|
|
>;
|
|
};
|
|
};
|
|
|
|
usart2 {
|
|
pinctrl_usart2: usart2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
|
|
AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
|
|
>;
|
|
};
|
|
pinctrl_usart2_rts: usart2_rts-0 {
|
|
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
|
|
};
|
|
pinctrl_usart2_cts: usart2_cts-0 {
|
|
atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
|
|
};
|
|
};
|
|
|
|
usart3 {
|
|
pinctrl_usart3: usart3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
|
|
AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
|
|
>;
|
|
};
|
|
};
|
|
|
|
usart4 {
|
|
pinctrl_usart4: usart4-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
|
|
AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
|
|
>;
|
|
};
|
|
pinctrl_usart4_rts: usart4_rts-0 {
|
|
atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
|
|
};
|
|
pinctrl_usart4_cts: usart4_cts-0 {
|
|
atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
|
|
};
|
|
};
|
|
};
|
|
|
|
aic: interrupt-controller@fc06e000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,sama5d4-aic";
|
|
interrupt-controller;
|
|
reg = <0xfc06e000 0x200>;
|
|
atmel,external-irqs = <56>;
|
|
};
|
|
};
|
|
};
|
|
};
|