514 lines
13 KiB
C
514 lines
13 KiB
C
/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/coresight.h>
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#include <linux/coresight-pmu.h>
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#include <linux/cpumask.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/perf_event.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "coresight-etm-perf.h"
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#include "coresight-priv.h"
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static struct pmu etm_pmu;
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static bool etm_perf_up;
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/**
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* struct etm_event_data - Coresight specifics associated to an event
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* @work: Handle to free allocated memory outside IRQ context.
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* @mask: Hold the CPU(s) this event was set for.
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* @snk_config: The sink configuration.
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* @path: An array of path, each slot for one CPU.
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*/
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struct etm_event_data {
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struct work_struct work;
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cpumask_t mask;
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void *snk_config;
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struct list_head **path;
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};
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static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
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static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
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/* ETMv3.5/PTM's ETMCR is 'config' */
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PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC));
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PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
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static struct attribute *etm_config_formats_attr[] = {
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&format_attr_cycacc.attr,
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&format_attr_timestamp.attr,
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NULL,
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};
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static struct attribute_group etm_pmu_format_group = {
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.name = "format",
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.attrs = etm_config_formats_attr,
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};
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static const struct attribute_group *etm_pmu_attr_groups[] = {
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&etm_pmu_format_group,
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NULL,
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};
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static void etm_event_read(struct perf_event *event) {}
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static int etm_addr_filters_alloc(struct perf_event *event)
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{
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struct etm_filters *filters;
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int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu);
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filters = kzalloc_node(sizeof(struct etm_filters), GFP_KERNEL, node);
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if (!filters)
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return -ENOMEM;
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if (event->parent)
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memcpy(filters, event->parent->hw.addr_filters,
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sizeof(*filters));
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event->hw.addr_filters = filters;
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return 0;
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}
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static void etm_event_destroy(struct perf_event *event)
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{
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kfree(event->hw.addr_filters);
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event->hw.addr_filters = NULL;
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}
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static int etm_event_init(struct perf_event *event)
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{
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int ret = 0;
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if (event->attr.type != etm_pmu.type) {
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ret = -ENOENT;
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goto out;
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}
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ret = etm_addr_filters_alloc(event);
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if (ret)
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goto out;
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event->destroy = etm_event_destroy;
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out:
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return ret;
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}
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static void free_event_data(struct work_struct *work)
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{
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int cpu;
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cpumask_t *mask;
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struct etm_event_data *event_data;
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struct coresight_device *sink;
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event_data = container_of(work, struct etm_event_data, work);
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mask = &event_data->mask;
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/*
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* First deal with the sink configuration. See comment in
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* etm_setup_aux() about why we take the first available path.
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*/
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if (event_data->snk_config) {
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cpu = cpumask_first(mask);
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sink = coresight_get_sink(event_data->path[cpu]);
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if (sink_ops(sink)->free_buffer)
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sink_ops(sink)->free_buffer(event_data->snk_config);
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}
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for_each_cpu(cpu, mask) {
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if (!(IS_ERR_OR_NULL(event_data->path[cpu])))
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coresight_release_path(event_data->path[cpu]);
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}
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kfree(event_data->path);
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kfree(event_data);
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}
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static void *alloc_event_data(int cpu)
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{
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int size;
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cpumask_t *mask;
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struct etm_event_data *event_data;
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/* First get memory for the session's data */
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event_data = kzalloc(sizeof(struct etm_event_data), GFP_KERNEL);
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if (!event_data)
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return NULL;
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/* Make sure nothing disappears under us */
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get_online_cpus();
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size = num_online_cpus();
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mask = &event_data->mask;
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if (cpu != -1)
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cpumask_set_cpu(cpu, mask);
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else
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cpumask_copy(mask, cpu_online_mask);
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put_online_cpus();
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/*
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* Each CPU has a single path between source and destination. As such
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* allocate an array using CPU numbers as indexes. That way a path
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* for any CPU can easily be accessed at any given time. We proceed
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* the same way for sessions involving a single CPU. The cost of
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* unused memory when dealing with single CPU trace scenarios is small
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* compared to the cost of searching through an optimized array.
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*/
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event_data->path = kcalloc(size,
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sizeof(struct list_head *), GFP_KERNEL);
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if (!event_data->path) {
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kfree(event_data);
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return NULL;
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}
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return event_data;
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}
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static void etm_free_aux(void *data)
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{
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struct etm_event_data *event_data = data;
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schedule_work(&event_data->work);
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}
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static void *etm_setup_aux(int event_cpu, void **pages,
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int nr_pages, bool overwrite)
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{
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int cpu;
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cpumask_t *mask;
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struct coresight_device *sink;
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struct etm_event_data *event_data = NULL;
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event_data = alloc_event_data(event_cpu);
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if (!event_data)
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return NULL;
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/*
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* In theory nothing prevent tracers in a trace session from being
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* associated with different sinks, nor having a sink per tracer. But
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* until we have HW with this kind of topology we need to assume tracers
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* in a trace session are using the same sink. Therefore go through
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* the coresight bus and pick the first enabled sink.
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*
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* When operated from sysFS users are responsible to enable the sink
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* while from perf, the perf tools will do it based on the choice made
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* on the cmd line. As such the "enable_sink" flag in sysFS is reset.
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*/
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sink = coresight_get_enabled_sink(true);
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if (!sink)
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goto err;
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INIT_WORK(&event_data->work, free_event_data);
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mask = &event_data->mask;
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/* Setup the path for each CPU in a trace session */
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for_each_cpu(cpu, mask) {
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struct coresight_device *csdev;
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csdev = per_cpu(csdev_src, cpu);
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if (!csdev)
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goto err;
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/*
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* Building a path doesn't enable it, it simply builds a
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* list of devices from source to sink that can be
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* referenced later when the path is actually needed.
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*/
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event_data->path[cpu] = coresight_build_path(csdev, sink);
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if (IS_ERR(event_data->path[cpu]))
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goto err;
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}
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if (!sink_ops(sink)->alloc_buffer)
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goto err;
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/* Get the AUX specific data from the sink buffer */
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event_data->snk_config =
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sink_ops(sink)->alloc_buffer(sink, cpu, pages,
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nr_pages, overwrite);
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if (!event_data->snk_config)
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goto err;
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out:
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return event_data;
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err:
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etm_free_aux(event_data);
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event_data = NULL;
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goto out;
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}
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static void etm_event_start(struct perf_event *event, int flags)
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{
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int cpu = smp_processor_id();
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struct etm_event_data *event_data;
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struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
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struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
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if (!csdev)
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goto fail;
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/*
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* Deal with the ring buffer API and get a handle on the
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* session's information.
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*/
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event_data = perf_aux_output_begin(handle, event);
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if (!event_data)
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goto fail;
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/* We need a sink, no need to continue without one */
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sink = coresight_get_sink(event_data->path[cpu]);
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if (WARN_ON_ONCE(!sink || !sink_ops(sink)->set_buffer))
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goto fail_end_stop;
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/* Configure the sink */
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if (sink_ops(sink)->set_buffer(sink, handle,
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event_data->snk_config))
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goto fail_end_stop;
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/* Nothing will happen without a path */
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if (coresight_enable_path(event_data->path[cpu], CS_MODE_PERF))
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goto fail_end_stop;
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/* Tell the perf core the event is alive */
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event->hw.state = 0;
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/* Finally enable the tracer */
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if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
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goto fail_end_stop;
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out:
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return;
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fail_end_stop:
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perf_aux_output_end(handle, 0, true);
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fail:
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event->hw.state = PERF_HES_STOPPED;
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goto out;
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}
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static void etm_event_stop(struct perf_event *event, int mode)
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{
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bool lost;
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int cpu = smp_processor_id();
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unsigned long size;
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struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
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struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
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struct etm_event_data *event_data = perf_get_aux(handle);
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if (event->hw.state == PERF_HES_STOPPED)
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return;
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if (!csdev)
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return;
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sink = coresight_get_sink(event_data->path[cpu]);
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if (!sink)
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return;
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/* stop tracer */
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source_ops(csdev)->disable(csdev, event);
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/* tell the core */
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event->hw.state = PERF_HES_STOPPED;
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if (mode & PERF_EF_UPDATE) {
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if (WARN_ON_ONCE(handle->event != event))
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return;
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/* update trace information */
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if (!sink_ops(sink)->update_buffer)
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return;
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sink_ops(sink)->update_buffer(sink, handle,
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event_data->snk_config);
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if (!sink_ops(sink)->reset_buffer)
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return;
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size = sink_ops(sink)->reset_buffer(sink, handle,
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event_data->snk_config,
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&lost);
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perf_aux_output_end(handle, size, lost);
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}
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/* Disabling the path make its elements available to other sessions */
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coresight_disable_path(event_data->path[cpu]);
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}
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static int etm_event_add(struct perf_event *event, int mode)
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{
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int ret = 0;
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struct hw_perf_event *hwc = &event->hw;
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if (mode & PERF_EF_START) {
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etm_event_start(event, 0);
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if (hwc->state & PERF_HES_STOPPED)
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ret = -EINVAL;
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} else {
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hwc->state = PERF_HES_STOPPED;
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}
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return ret;
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}
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static void etm_event_del(struct perf_event *event, int mode)
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{
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etm_event_stop(event, PERF_EF_UPDATE);
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}
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static int etm_addr_filters_validate(struct list_head *filters)
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{
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bool range = false, address = false;
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int index = 0;
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struct perf_addr_filter *filter;
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list_for_each_entry(filter, filters, entry) {
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/*
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* No need to go further if there's no more
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* room for filters.
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*/
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if (++index > ETM_ADDR_CMP_MAX)
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return -EOPNOTSUPP;
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/*
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* As taken from the struct perf_addr_filter documentation:
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* @range: 1: range, 0: address
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*
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* At this time we don't allow range and start/stop filtering
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* to cohabitate, they have to be mutually exclusive.
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*/
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if ((filter->range == 1) && address)
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return -EOPNOTSUPP;
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if ((filter->range == 0) && range)
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return -EOPNOTSUPP;
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/*
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* For range filtering, the second address in the address
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* range comparator needs to be higher than the first.
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* Invalid otherwise.
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*/
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if (filter->range && filter->size == 0)
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return -EINVAL;
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/*
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* Everything checks out with this filter, record what we've
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* received before moving on to the next one.
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*/
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if (filter->range)
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range = true;
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else
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address = true;
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}
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return 0;
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}
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static void etm_addr_filters_sync(struct perf_event *event)
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{
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struct perf_addr_filters_head *head = perf_event_addr_filters(event);
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unsigned long start, stop, *offs = event->addr_filters_offs;
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struct etm_filters *filters = event->hw.addr_filters;
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struct etm_filter *etm_filter;
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struct perf_addr_filter *filter;
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int i = 0;
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list_for_each_entry(filter, &head->list, entry) {
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start = filter->offset + offs[i];
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stop = start + filter->size;
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etm_filter = &filters->etm_filter[i];
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if (filter->range == 1) {
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etm_filter->start_addr = start;
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etm_filter->stop_addr = stop;
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etm_filter->type = ETM_ADDR_TYPE_RANGE;
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} else {
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if (filter->filter == 1) {
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etm_filter->start_addr = start;
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etm_filter->type = ETM_ADDR_TYPE_START;
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} else {
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etm_filter->stop_addr = stop;
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etm_filter->type = ETM_ADDR_TYPE_STOP;
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}
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}
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i++;
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}
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filters->nr_filters = i;
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}
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int etm_perf_symlink(struct coresight_device *csdev, bool link)
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{
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char entry[sizeof("cpu9999999")];
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int ret = 0, cpu = source_ops(csdev)->cpu_id(csdev);
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struct device *pmu_dev = etm_pmu.dev;
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struct device *cs_dev = &csdev->dev;
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sprintf(entry, "cpu%d", cpu);
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if (!etm_perf_up)
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return -EPROBE_DEFER;
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if (link) {
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ret = sysfs_create_link(&pmu_dev->kobj, &cs_dev->kobj, entry);
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if (ret)
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return ret;
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per_cpu(csdev_src, cpu) = csdev;
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} else {
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sysfs_remove_link(&pmu_dev->kobj, entry);
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per_cpu(csdev_src, cpu) = NULL;
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}
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return 0;
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}
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static int __init etm_perf_init(void)
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{
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int ret;
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etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE;
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etm_pmu.attr_groups = etm_pmu_attr_groups;
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etm_pmu.task_ctx_nr = perf_sw_context;
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etm_pmu.read = etm_event_read;
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etm_pmu.event_init = etm_event_init;
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etm_pmu.setup_aux = etm_setup_aux;
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etm_pmu.free_aux = etm_free_aux;
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etm_pmu.start = etm_event_start;
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etm_pmu.stop = etm_event_stop;
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etm_pmu.add = etm_event_add;
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etm_pmu.del = etm_event_del;
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etm_pmu.addr_filters_sync = etm_addr_filters_sync;
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etm_pmu.addr_filters_validate = etm_addr_filters_validate;
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etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX;
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ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1);
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if (ret == 0)
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etm_perf_up = true;
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return ret;
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}
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device_initcall(etm_perf_init);
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