152 lines
3.8 KiB
C
152 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copied from arch/arm64/kernel/cpufeature.c
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*
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* Copyright (C) 2015 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/bitmap.h>
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#include <linux/of.h>
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#include <asm/processor.h>
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#include <asm/hwcap.h>
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#include <asm/smp.h>
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#include <asm/switch_to.h>
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unsigned long elf_hwcap __read_mostly;
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/* Host ISA bitmap */
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static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
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#ifdef CONFIG_FPU
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bool has_fpu __read_mostly;
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#endif
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/**
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* riscv_isa_extension_base() - Get base extension word
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*
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* @isa_bitmap: ISA bitmap to use
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* Return: base extension word as unsigned long value
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
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{
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if (!isa_bitmap)
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return riscv_isa[0];
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return isa_bitmap[0];
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}
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EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
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/**
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* __riscv_isa_extension_available() - Check whether given extension
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* is available or not
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*
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* @isa_bitmap: ISA bitmap to use
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* @bit: bit position of the desired extension
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* Return: true or false
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
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{
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const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
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if (bit >= RISCV_ISA_EXT_MAX)
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return false;
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return test_bit(bit, bmap) ? true : false;
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}
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EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
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void riscv_fill_hwcap(void)
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{
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struct device_node *node;
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const char *isa;
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char print_str[BITS_PER_LONG + 1];
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size_t i, j, isa_len;
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static unsigned long isa2hwcap[256] = {0};
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isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
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isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
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isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
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isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
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isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
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isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
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elf_hwcap = 0;
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bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
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for_each_of_cpu_node(node) {
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unsigned long this_hwcap = 0;
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unsigned long this_isa = 0;
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if (riscv_of_processor_hartid(node) < 0)
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continue;
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if (of_property_read_string(node, "riscv,isa", &isa)) {
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pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
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continue;
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}
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i = 0;
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isa_len = strlen(isa);
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#if IS_ENABLED(CONFIG_32BIT)
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if (!strncmp(isa, "rv32", 4))
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i += 4;
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#elif IS_ENABLED(CONFIG_64BIT)
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if (!strncmp(isa, "rv64", 4))
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i += 4;
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#endif
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for (; i < isa_len; ++i) {
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this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
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/*
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* TODO: X, Y and Z extension parsing for Host ISA
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* bitmap will be added in-future.
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*/
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if ('a' <= isa[i] && isa[i] < 'x')
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this_isa |= (1UL << (isa[i] - 'a'));
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}
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/*
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* All "okay" hart should have same isa. Set HWCAP based on
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* common capabilities of every "okay" hart, in case they don't
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* have.
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*/
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if (elf_hwcap)
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elf_hwcap &= this_hwcap;
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else
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elf_hwcap = this_hwcap;
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if (riscv_isa[0])
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riscv_isa[0] &= this_isa;
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else
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riscv_isa[0] = this_isa;
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}
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/* We don't support systems with F but without D, so mask those out
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* here. */
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if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
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pr_info("This kernel does not support systems with F but not D\n");
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elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
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}
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memset(print_str, 0, sizeof(print_str));
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for (i = 0, j = 0; i < BITS_PER_LONG; i++)
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if (riscv_isa[0] & BIT_MASK(i))
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print_str[j++] = (char)('a' + i);
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pr_info("riscv: ISA extensions %s\n", print_str);
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memset(print_str, 0, sizeof(print_str));
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for (i = 0, j = 0; i < BITS_PER_LONG; i++)
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if (elf_hwcap & BIT_MASK(i))
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print_str[j++] = (char)('a' + i);
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pr_info("riscv: ELF capabilities %s\n", print_str);
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#ifdef CONFIG_FPU
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if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
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has_fpu = true;
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#endif
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}
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