748 lines
21 KiB
C
748 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copied from arch/arm64/kernel/cpufeature.c
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*
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* Copyright (C) 2015 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/acpi.h>
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#include <linux/bitmap.h>
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#include <linux/ctype.h>
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#include <linux/log2.h>
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#include <linux/memory.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <asm/acpi.h>
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#include <asm/alternative.h>
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#include <asm/cacheflush.h>
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#include <asm/cpufeature.h>
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#include <asm/hwcap.h>
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#include <asm/hwprobe.h>
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#include <asm/patch.h>
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#include <asm/processor.h>
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#include <asm/sbi.h>
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#include <asm/vector.h>
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#include "copy-unaligned.h"
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#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
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#define MISALIGNED_ACCESS_JIFFIES_LG2 1
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#define MISALIGNED_BUFFER_SIZE 0x4000
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#define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
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unsigned long elf_hwcap __read_mostly;
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/* Host ISA bitmap */
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static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
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/* Per-cpu ISA extensions. */
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struct riscv_isainfo hart_isa[NR_CPUS];
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/* Performance information */
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DEFINE_PER_CPU(long, misaligned_access_speed);
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/**
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* riscv_isa_extension_base() - Get base extension word
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*
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* @isa_bitmap: ISA bitmap to use
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* Return: base extension word as unsigned long value
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
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{
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if (!isa_bitmap)
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return riscv_isa[0];
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return isa_bitmap[0];
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}
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EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
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/**
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* __riscv_isa_extension_available() - Check whether given extension
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* is available or not
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*
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* @isa_bitmap: ISA bitmap to use
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* @bit: bit position of the desired extension
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* Return: true or false
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
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{
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const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
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if (bit >= RISCV_ISA_EXT_MAX)
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return false;
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return test_bit(bit, bmap) ? true : false;
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}
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EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
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static bool riscv_isa_extension_check(int id)
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{
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switch (id) {
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case RISCV_ISA_EXT_ZICBOM:
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if (!riscv_cbom_block_size) {
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pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
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return false;
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} else if (!is_power_of_2(riscv_cbom_block_size)) {
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pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
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return false;
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}
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return true;
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case RISCV_ISA_EXT_ZICBOZ:
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if (!riscv_cboz_block_size) {
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pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
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return false;
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} else if (!is_power_of_2(riscv_cboz_block_size)) {
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pr_err("cboz-block-size present, but is not a power-of-2\n");
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return false;
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}
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return true;
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}
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return true;
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}
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#define __RISCV_ISA_EXT_DATA(_name, _id) { \
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.name = #_name, \
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.property = #_name, \
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.id = _id, \
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}
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/*
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* The canonical order of ISA extension names in the ISA string is defined in
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* chapter 27 of the unprivileged specification.
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*
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* Ordinarily, for in-kernel data structures, this order is unimportant but
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* isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
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*
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* The specification uses vague wording, such as should, when it comes to
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* ordering, so for our purposes the following rules apply:
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*
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* 1. All multi-letter extensions must be separated from other extensions by an
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* underscore.
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*
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* 2. Additional standard extensions (starting with 'Z') must be sorted after
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* single-letter extensions and before any higher-privileged extensions.
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*
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* 3. The first letter following the 'Z' conventionally indicates the most
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* closely related alphabetical extension category, IMAFDQLCBKJTPVH.
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* If multiple 'Z' extensions are named, they must be ordered first by
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* category, then alphabetically within a category.
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*
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* 3. Standard supervisor-level extensions (starting with 'S') must be listed
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* after standard unprivileged extensions. If multiple supervisor-level
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* extensions are listed, they must be ordered alphabetically.
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*
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* 4. Standard machine-level extensions (starting with 'Zxm') must be listed
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* after any lower-privileged, standard extensions. If multiple
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* machine-level extensions are listed, they must be ordered
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* alphabetically.
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*
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* 5. Non-standard extensions (starting with 'X') must be listed after all
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* standard extensions. If multiple non-standard extensions are listed, they
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* must be ordered alphabetically.
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*
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* An example string following the order is:
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* rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
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*
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* New entries to this struct should follow the ordering rules described above.
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*/
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const struct riscv_isa_ext_data riscv_isa_ext[] = {
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__RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
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__RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
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__RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
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__RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
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__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
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__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
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__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
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__RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b),
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__RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k),
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__RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j),
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__RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p),
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__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
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__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
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__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
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__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
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__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
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__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
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__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
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__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
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__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
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__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
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__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
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__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
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__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
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__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
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__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
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__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
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__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
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__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
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__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
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};
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const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
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static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo,
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unsigned long *isa2hwcap, const char *isa)
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{
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/*
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* For all possible cpus, we have already validated in
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* the boot process that they at least contain "rv" and
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* whichever of "32"/"64" this kernel supports, and so this
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* section can be skipped.
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*/
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isa += 4;
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while (*isa) {
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const char *ext = isa++;
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const char *ext_end = isa;
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bool ext_long = false, ext_err = false;
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switch (*ext) {
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case 's':
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/*
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* Workaround for invalid single-letter 's' & 'u'(QEMU).
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* No need to set the bit in riscv_isa as 's' & 'u' are
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* not valid ISA extensions. It works until multi-letter
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* extension starting with "Su" appears.
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*/
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if (ext[-1] != '_' && ext[1] == 'u') {
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++isa;
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ext_err = true;
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break;
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}
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fallthrough;
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case 'S':
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case 'x':
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case 'X':
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case 'z':
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case 'Z':
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/*
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* Before attempting to parse the extension itself, we find its end.
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* As multi-letter extensions must be split from other multi-letter
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* extensions with an "_", the end of a multi-letter extension will
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* either be the null character or the "_" at the start of the next
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* multi-letter extension.
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*
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* Next, as the extensions version is currently ignored, we
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* eliminate that portion. This is done by parsing backwards from
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* the end of the extension, removing any numbers. This may be a
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* major or minor number however, so the process is repeated if a
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* minor number was found.
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*
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* ext_end is intended to represent the first character *after* the
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* name portion of an extension, but will be decremented to the last
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* character itself while eliminating the extensions version number.
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* A simple re-increment solves this problem.
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*/
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ext_long = true;
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for (; *isa && *isa != '_'; ++isa)
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if (unlikely(!isalnum(*isa)))
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ext_err = true;
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ext_end = isa;
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if (unlikely(ext_err))
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break;
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if (!isdigit(ext_end[-1]))
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break;
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while (isdigit(*--ext_end))
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;
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if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
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++ext_end;
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break;
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}
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while (isdigit(*--ext_end))
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;
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++ext_end;
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break;
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default:
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/*
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* Things are a little easier for single-letter extensions, as they
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* are parsed forwards.
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*
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* After checking that our starting position is valid, we need to
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* ensure that, when isa was incremented at the start of the loop,
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* that it arrived at the start of the next extension.
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*
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* If we are already on a non-digit, there is nothing to do. Either
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* we have a multi-letter extension's _, or the start of an
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* extension.
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*
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* Otherwise we have found the current extension's major version
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* number. Parse past it, and a subsequent p/minor version number
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* if present. The `p` extension must not appear immediately after
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* a number, so there is no fear of missing it.
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*
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*/
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if (unlikely(!isalpha(*ext))) {
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ext_err = true;
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break;
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}
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if (!isdigit(*isa))
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break;
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while (isdigit(*++isa))
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;
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if (tolower(*isa) != 'p')
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break;
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if (!isdigit(*++isa)) {
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--isa;
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break;
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}
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while (isdigit(*++isa))
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;
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break;
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}
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/*
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* The parser expects that at the start of an iteration isa points to the
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* first character of the next extension. As we stop parsing an extension
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* on meeting a non-alphanumeric character, an extra increment is needed
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* where the succeeding extension is a multi-letter prefixed with an "_".
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*/
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if (*isa == '_')
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++isa;
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#define SET_ISA_EXT_MAP(name, bit) \
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do { \
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if ((ext_end - ext == strlen(name)) && \
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!strncasecmp(ext, name, strlen(name)) && \
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riscv_isa_extension_check(bit)) \
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set_bit(bit, isainfo->isa); \
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} while (false) \
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if (unlikely(ext_err))
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continue;
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if (!ext_long) {
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int nr = tolower(*ext) - 'a';
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if (riscv_isa_extension_check(nr)) {
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*this_hwcap |= isa2hwcap[nr];
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set_bit(nr, isainfo->isa);
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}
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} else {
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for (int i = 0; i < riscv_isa_ext_count; i++)
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SET_ISA_EXT_MAP(riscv_isa_ext[i].name,
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riscv_isa_ext[i].id);
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}
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#undef SET_ISA_EXT_MAP
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}
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}
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static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
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{
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struct device_node *node;
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const char *isa;
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int rc;
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struct acpi_table_header *rhct;
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acpi_status status;
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unsigned int cpu;
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if (!acpi_disabled) {
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status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
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if (ACPI_FAILURE(status))
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return;
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}
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for_each_possible_cpu(cpu) {
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struct riscv_isainfo *isainfo = &hart_isa[cpu];
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unsigned long this_hwcap = 0;
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if (acpi_disabled) {
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node = of_cpu_device_node_get(cpu);
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if (!node) {
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pr_warn("Unable to find cpu node\n");
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continue;
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}
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rc = of_property_read_string(node, "riscv,isa", &isa);
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of_node_put(node);
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if (rc) {
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pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
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continue;
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}
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} else {
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rc = acpi_get_riscv_isa(rhct, cpu, &isa);
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if (rc < 0) {
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pr_warn("Unable to get ISA for the hart - %d\n", cpu);
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continue;
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}
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}
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riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa);
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/*
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* These ones were as they were part of the base ISA when the
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* port & dt-bindings were upstreamed, and so can be set
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* unconditionally where `i` is in riscv,isa on DT systems.
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*/
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if (acpi_disabled) {
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set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
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set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
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set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
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set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
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}
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/*
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* "V" in ISA strings is ambiguous in practice: it should mean
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* just the standard V-1.0 but vendors aren't well behaved.
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* Many vendors with T-Head CPU cores which implement the 0.7.1
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* version of the vector specification put "v" into their DTs.
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* CPU cores with the ratified spec will contain non-zero
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* marchid.
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*/
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if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID &&
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riscv_cached_marchid(cpu) == 0x0) {
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this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
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clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
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}
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/*
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* All "okay" hart should have same isa. Set HWCAP based on
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* common capabilities of every "okay" hart, in case they don't
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* have.
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*/
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if (elf_hwcap)
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elf_hwcap &= this_hwcap;
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else
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elf_hwcap = this_hwcap;
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if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
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bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
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else
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bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
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}
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if (!acpi_disabled && rhct)
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acpi_put_table((struct acpi_table_header *)rhct);
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}
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static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
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{
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unsigned int cpu;
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for_each_possible_cpu(cpu) {
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unsigned long this_hwcap = 0;
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struct device_node *cpu_node;
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struct riscv_isainfo *isainfo = &hart_isa[cpu];
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node) {
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pr_warn("Unable to find cpu node\n");
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continue;
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}
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if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
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of_node_put(cpu_node);
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continue;
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}
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for (int i = 0; i < riscv_isa_ext_count; i++) {
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if (of_property_match_string(cpu_node, "riscv,isa-extensions",
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riscv_isa_ext[i].property) < 0)
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continue;
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if (!riscv_isa_extension_check(riscv_isa_ext[i].id))
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continue;
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/* Only single letter extensions get set in hwcap */
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if (strnlen(riscv_isa_ext[i].name, 2) == 1)
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this_hwcap |= isa2hwcap[riscv_isa_ext[i].id];
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set_bit(riscv_isa_ext[i].id, isainfo->isa);
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}
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of_node_put(cpu_node);
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/*
|
|
* All "okay" harts should have same isa. Set HWCAP based on
|
|
* common capabilities of every "okay" hart, in case they don't.
|
|
*/
|
|
if (elf_hwcap)
|
|
elf_hwcap &= this_hwcap;
|
|
else
|
|
elf_hwcap = this_hwcap;
|
|
|
|
if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
|
|
bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
|
|
else
|
|
bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
|
|
}
|
|
|
|
if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
|
|
return -ENOENT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_RISCV_ISA_FALLBACK
|
|
bool __initdata riscv_isa_fallback = true;
|
|
#else
|
|
bool __initdata riscv_isa_fallback;
|
|
static int __init riscv_isa_fallback_setup(char *__unused)
|
|
{
|
|
riscv_isa_fallback = true;
|
|
return 1;
|
|
}
|
|
early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
|
|
#endif
|
|
|
|
void __init riscv_fill_hwcap(void)
|
|
{
|
|
char print_str[NUM_ALPHA_EXTS + 1];
|
|
unsigned long isa2hwcap[26] = {0};
|
|
int i, j;
|
|
|
|
isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
|
|
isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
|
|
isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
|
|
isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
|
|
isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
|
|
isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
|
|
isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
|
|
|
|
if (!acpi_disabled) {
|
|
riscv_fill_hwcap_from_isa_string(isa2hwcap);
|
|
} else {
|
|
int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
|
|
|
|
if (ret && riscv_isa_fallback) {
|
|
pr_info("Falling back to deprecated \"riscv,isa\"\n");
|
|
riscv_fill_hwcap_from_isa_string(isa2hwcap);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* We don't support systems with F but without D, so mask those out
|
|
* here.
|
|
*/
|
|
if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
|
|
pr_info("This kernel does not support systems with F but not D\n");
|
|
elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
|
|
}
|
|
|
|
if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
|
|
riscv_v_setup_vsize();
|
|
/*
|
|
* ISA string in device tree might have 'v' flag, but
|
|
* CONFIG_RISCV_ISA_V is disabled in kernel.
|
|
* Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
|
|
*/
|
|
if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
|
|
elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
|
|
}
|
|
|
|
memset(print_str, 0, sizeof(print_str));
|
|
for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
|
|
if (riscv_isa[0] & BIT_MASK(i))
|
|
print_str[j++] = (char)('a' + i);
|
|
pr_info("riscv: base ISA extensions %s\n", print_str);
|
|
|
|
memset(print_str, 0, sizeof(print_str));
|
|
for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
|
|
if (elf_hwcap & BIT_MASK(i))
|
|
print_str[j++] = (char)('a' + i);
|
|
pr_info("riscv: ELF capabilities %s\n", print_str);
|
|
}
|
|
|
|
unsigned long riscv_get_elf_hwcap(void)
|
|
{
|
|
unsigned long hwcap;
|
|
|
|
hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
|
|
|
|
if (!riscv_v_vstate_ctrl_user_allowed())
|
|
hwcap &= ~COMPAT_HWCAP_ISA_V;
|
|
|
|
return hwcap;
|
|
}
|
|
|
|
void check_unaligned_access(int cpu)
|
|
{
|
|
u64 start_cycles, end_cycles;
|
|
u64 word_cycles;
|
|
u64 byte_cycles;
|
|
int ratio;
|
|
unsigned long start_jiffies, now;
|
|
struct page *page;
|
|
void *dst;
|
|
void *src;
|
|
long speed = RISCV_HWPROBE_MISALIGNED_SLOW;
|
|
|
|
/* We are already set since the last check */
|
|
if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN)
|
|
return;
|
|
|
|
page = alloc_pages(GFP_NOWAIT, get_order(MISALIGNED_BUFFER_SIZE));
|
|
if (!page) {
|
|
pr_warn("Can't alloc pages to measure memcpy performance");
|
|
return;
|
|
}
|
|
|
|
/* Make an unaligned destination buffer. */
|
|
dst = (void *)((unsigned long)page_address(page) | 0x1);
|
|
/* Unalign src as well, but differently (off by 1 + 2 = 3). */
|
|
src = dst + (MISALIGNED_BUFFER_SIZE / 2);
|
|
src += 2;
|
|
word_cycles = -1ULL;
|
|
/* Do a warmup. */
|
|
__riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE);
|
|
preempt_disable();
|
|
start_jiffies = jiffies;
|
|
while ((now = jiffies) == start_jiffies)
|
|
cpu_relax();
|
|
|
|
/*
|
|
* For a fixed amount of time, repeatedly try the function, and take
|
|
* the best time in cycles as the measurement.
|
|
*/
|
|
while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) {
|
|
start_cycles = get_cycles64();
|
|
/* Ensure the CSR read can't reorder WRT to the copy. */
|
|
mb();
|
|
__riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE);
|
|
/* Ensure the copy ends before the end time is snapped. */
|
|
mb();
|
|
end_cycles = get_cycles64();
|
|
if ((end_cycles - start_cycles) < word_cycles)
|
|
word_cycles = end_cycles - start_cycles;
|
|
}
|
|
|
|
byte_cycles = -1ULL;
|
|
__riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE);
|
|
start_jiffies = jiffies;
|
|
while ((now = jiffies) == start_jiffies)
|
|
cpu_relax();
|
|
|
|
while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) {
|
|
start_cycles = get_cycles64();
|
|
mb();
|
|
__riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE);
|
|
mb();
|
|
end_cycles = get_cycles64();
|
|
if ((end_cycles - start_cycles) < byte_cycles)
|
|
byte_cycles = end_cycles - start_cycles;
|
|
}
|
|
|
|
preempt_enable();
|
|
|
|
/* Don't divide by zero. */
|
|
if (!word_cycles || !byte_cycles) {
|
|
pr_warn("cpu%d: rdtime lacks granularity needed to measure unaligned access speed\n",
|
|
cpu);
|
|
|
|
goto out;
|
|
}
|
|
|
|
if (word_cycles < byte_cycles)
|
|
speed = RISCV_HWPROBE_MISALIGNED_FAST;
|
|
|
|
ratio = div_u64((byte_cycles * 100), word_cycles);
|
|
pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.%02d, unaligned accesses are %s\n",
|
|
cpu,
|
|
ratio / 100,
|
|
ratio % 100,
|
|
(speed == RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow");
|
|
|
|
per_cpu(misaligned_access_speed, cpu) = speed;
|
|
|
|
out:
|
|
__free_pages(page, get_order(MISALIGNED_BUFFER_SIZE));
|
|
}
|
|
|
|
static int check_unaligned_access_boot_cpu(void)
|
|
{
|
|
check_unaligned_access(0);
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(check_unaligned_access_boot_cpu);
|
|
|
|
#ifdef CONFIG_RISCV_ALTERNATIVE
|
|
/*
|
|
* Alternative patch sites consider 48 bits when determining when to patch
|
|
* the old instruction sequence with the new. These bits are broken into a
|
|
* 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
|
|
* patch site is for an erratum, identified by the 32-bit patch ID. When
|
|
* the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
|
|
* further break down patch ID into two 16-bit numbers. The lower 16 bits
|
|
* are the cpufeature ID and the upper 16 bits are used for a value specific
|
|
* to the cpufeature and patch site. If the upper 16 bits are zero, then it
|
|
* implies no specific value is specified. cpufeatures that want to control
|
|
* patching on a per-site basis will provide non-zero values and implement
|
|
* checks here. The checks return true when patching should be done, and
|
|
* false otherwise.
|
|
*/
|
|
static bool riscv_cpufeature_patch_check(u16 id, u16 value)
|
|
{
|
|
if (!value)
|
|
return true;
|
|
|
|
switch (id) {
|
|
case RISCV_ISA_EXT_ZICBOZ:
|
|
/*
|
|
* Zicboz alternative applications provide the maximum
|
|
* supported block size order, or zero when it doesn't
|
|
* matter. If the current block size exceeds the maximum,
|
|
* then the alternative cannot be applied.
|
|
*/
|
|
return riscv_cboz_block_size <= (1U << value);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
|
|
struct alt_entry *end,
|
|
unsigned int stage)
|
|
{
|
|
struct alt_entry *alt;
|
|
void *oldptr, *altptr;
|
|
u16 id, value;
|
|
|
|
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
|
|
return;
|
|
|
|
for (alt = begin; alt < end; alt++) {
|
|
if (alt->vendor_id != 0)
|
|
continue;
|
|
|
|
id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
|
|
|
|
if (id >= RISCV_ISA_EXT_MAX) {
|
|
WARN(1, "This extension id:%d is not in ISA extension list", id);
|
|
continue;
|
|
}
|
|
|
|
if (!__riscv_isa_extension_available(NULL, id))
|
|
continue;
|
|
|
|
value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
|
|
if (!riscv_cpufeature_patch_check(id, value))
|
|
continue;
|
|
|
|
oldptr = ALT_OLD_PTR(alt);
|
|
altptr = ALT_ALT_PTR(alt);
|
|
|
|
mutex_lock(&text_mutex);
|
|
patch_text_nosync(oldptr, altptr, alt->alt_len);
|
|
riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
|
|
mutex_unlock(&text_mutex);
|
|
}
|
|
}
|
|
#endif
|