318 lines
8.6 KiB
C
318 lines
8.6 KiB
C
/*
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* Root interrupt controller for the BCM2836 (Raspberry Pi 2).
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*
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* Copyright 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/cpu.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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#define LOCAL_CONTROL 0x000
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#define LOCAL_PRESCALER 0x008
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/*
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* The low 2 bits identify the CPU that the GPU IRQ goes to, and the
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* next 2 bits identify the CPU that the GPU FIQ goes to.
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*/
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#define LOCAL_GPU_ROUTING 0x00c
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/* When setting bits 0-3, enables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_SET 0x010
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/* When setting bits 0-3, disables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_CLR 0x014
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/*
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* The low 4 bits of this are the CPU's timer IRQ enables, and the
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* next 4 bits are the CPU's timer FIQ enables (which override the IRQ
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* bits).
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*/
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#define LOCAL_TIMER_INT_CONTROL0 0x040
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/*
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* The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
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* the next 4 bits are the CPU's per-mailbox FIQ enables (which
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* override the IRQ bits).
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*/
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#define LOCAL_MAILBOX_INT_CONTROL0 0x050
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/*
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* The CPU's interrupt status register. Bits are defined by the the
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* LOCAL_IRQ_* bits below.
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*/
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#define LOCAL_IRQ_PENDING0 0x060
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/* Same status bits as above, but for FIQ. */
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#define LOCAL_FIQ_PENDING0 0x070
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/*
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* Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
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* these bits are organized by mailbox number and then CPU number. We
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* use mailbox 0 for IPIs. The mailbox's interrupt is raised while
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* any bit is set.
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*/
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#define LOCAL_MAILBOX0_SET0 0x080
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#define LOCAL_MAILBOX3_SET0 0x08c
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/* Mailbox write-to-clear bits. */
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#define LOCAL_MAILBOX0_CLR0 0x0c0
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#define LOCAL_MAILBOX3_CLR0 0x0cc
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#define LOCAL_IRQ_CNTPSIRQ 0
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#define LOCAL_IRQ_CNTPNSIRQ 1
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#define LOCAL_IRQ_CNTHPIRQ 2
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#define LOCAL_IRQ_CNTVIRQ 3
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#define LOCAL_IRQ_MAILBOX0 4
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#define LOCAL_IRQ_MAILBOX1 5
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#define LOCAL_IRQ_MAILBOX2 6
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#define LOCAL_IRQ_MAILBOX3 7
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#define LOCAL_IRQ_GPU_FAST 8
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#define LOCAL_IRQ_PMU_FAST 9
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#define LAST_IRQ LOCAL_IRQ_PMU_FAST
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struct bcm2836_arm_irqchip_intc {
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struct irq_domain *domain;
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void __iomem *base;
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};
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static struct bcm2836_arm_irqchip_intc intc __read_mostly;
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static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
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unsigned int bit,
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int cpu)
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{
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void __iomem *reg = intc.base + reg_offset + 4 * cpu;
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writel(readl(reg) & ~BIT(bit), reg);
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}
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static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
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unsigned int bit,
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int cpu)
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{
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void __iomem *reg = intc.base + reg_offset + 4 * cpu;
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writel(readl(reg) | BIT(bit), reg);
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}
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static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
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{
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bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
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d->hwirq - LOCAL_IRQ_CNTPSIRQ,
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smp_processor_id());
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}
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static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
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{
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bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
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d->hwirq - LOCAL_IRQ_CNTPSIRQ,
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smp_processor_id());
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}
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static struct irq_chip bcm2836_arm_irqchip_timer = {
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.name = "bcm2836-timer",
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.irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
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.irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
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};
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static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
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{
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writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
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}
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static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
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{
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writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
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}
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static struct irq_chip bcm2836_arm_irqchip_pmu = {
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.name = "bcm2836-pmu",
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.irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
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.irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
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};
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static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
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{
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}
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static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
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{
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}
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static struct irq_chip bcm2836_arm_irqchip_gpu = {
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.name = "bcm2836-gpu",
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.irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
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.irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
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};
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static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip)
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{
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int irq = irq_create_mapping(intc.domain, hwirq);
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irq_set_percpu_devid(irq);
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irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
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irq_set_status_flags(irq, IRQ_NOAUTOEN);
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}
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static void
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__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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u32 stat;
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stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
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if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
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#ifdef CONFIG_SMP
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void __iomem *mailbox0 = (intc.base +
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LOCAL_MAILBOX0_CLR0 + 16 * cpu);
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u32 mbox_val = readl(mailbox0);
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u32 ipi = ffs(mbox_val) - 1;
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writel(1 << ipi, mailbox0);
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handle_IPI(ipi, regs);
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#endif
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} else if (stat) {
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u32 hwirq = ffs(stat) - 1;
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handle_domain_irq(intc.domain, hwirq, regs);
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}
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}
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#ifdef CONFIG_SMP
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static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
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unsigned int ipi)
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{
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int cpu;
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void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
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/*
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* Ensure that stores to normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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smp_wmb();
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for_each_cpu(cpu, mask) {
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writel(1 << ipi, mailbox0_base + 16 * cpu);
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}
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}
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static int bcm2836_cpu_starting(unsigned int cpu)
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{
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bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
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cpu);
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return 0;
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}
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static int bcm2836_cpu_dying(unsigned int cpu)
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{
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bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
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cpu);
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return 0;
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}
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#ifdef CONFIG_ARM
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static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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unsigned long secondary_startup_phys =
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(unsigned long)virt_to_phys((void *)secondary_startup);
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writel(secondary_startup_phys,
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intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
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return 0;
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}
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static const struct smp_operations bcm2836_smp_ops __initconst = {
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.smp_boot_secondary = bcm2836_smp_boot_secondary,
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};
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#endif
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#endif
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static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
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.xlate = irq_domain_xlate_onecell
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};
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static void
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bcm2836_arm_irqchip_smp_init(void)
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{
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#ifdef CONFIG_SMP
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/* Unmask IPIs to the boot CPU. */
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cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
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"irqchip/bcm2836:starting", bcm2836_cpu_starting,
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bcm2836_cpu_dying);
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set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
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#ifdef CONFIG_ARM
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smp_set_ops(&bcm2836_smp_ops);
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#endif
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#endif
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}
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/*
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* The LOCAL_IRQ_CNT* timer firings are based off of the external
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* oscillator with some scaling. The firmware sets up CNTFRQ to
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* report 19.2Mhz, but doesn't set up the scaling registers.
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*/
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static void bcm2835_init_local_timer_frequency(void)
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{
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/*
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* Set the timer to source from the 19.2Mhz crystal clock (bit
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* 8 unset), and only increment by 1 instead of 2 (bit 9
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* unset).
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*/
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writel(0, intc.base + LOCAL_CONTROL);
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/*
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* Set the timer prescaler to 1:1 (timer freq = input freq *
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* 2**31 / prescaler)
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*/
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writel(0x80000000, intc.base + LOCAL_PRESCALER);
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}
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static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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intc.base = of_iomap(node, 0);
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if (!intc.base) {
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panic("%s: unable to map local interrupt registers\n",
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node->full_name);
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}
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bcm2835_init_local_timer_frequency();
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intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
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&bcm2836_arm_irqchip_intc_ops,
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NULL);
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if (!intc.domain)
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panic("%s: unable to create IRQ domain\n", node->full_name);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
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&bcm2836_arm_irqchip_gpu);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
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&bcm2836_arm_irqchip_pmu);
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bcm2836_arm_irqchip_smp_init();
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set_handle_irq(bcm2836_arm_irqchip_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
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bcm2836_arm_irqchip_l1_intc_of_init);
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