OpenCloudOS-Kernel/drivers/cxl
Dan Williams e08063fb87 cxl/mem: Drop DVSEC vs EFI Memory Map sanity check
When the driver finds legacy DVSEC ranges active on a CXL Memory
Expander it indicates that platform firmware is not aware of, or is
deliberately disabling common CXL 2.0 operation. In this case Linux
generally has no choice, but to leave the device alone.

The driver attempts to validate that the DVSEC range is in the EFI
memory map. Remove that logic since there is no requirement that the
BIOS publish DVSEC ranges in the EFI Memory Map.

In the future the driver will want to permanently reserve this capacity
out of the available CFMWS capacity and hide it from
request_free_mem_region(), but it serves no purpose to warn about the
range not appearing in the EFI Memory Map.

Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164730734246.3806189.13995924771963139898.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-04-12 19:11:57 -07:00
..
core cxl/mbox: Use new return_code handling 2022-04-12 16:07:02 -07:00
Kconfig cxl/mem: Add the cxl_mem driver 2022-02-08 22:57:32 -08:00
Makefile cxl/mem: Add the cxl_mem driver 2022-02-08 22:57:32 -08:00
acpi.c cxl/core/port: Fix / relax decoder target enumeration 2022-02-08 23:15:10 -08:00
cxl.h cxl/core/port: Add endpoint decoders 2022-02-08 22:57:32 -08:00
cxlmem.h cxl/mbox: Improve handling of mbox_cmd hw return codes 2022-04-12 16:07:02 -07:00
cxlpci.h cxl/pci: Retrieve CXL DVSEC memory info 2022-02-08 22:57:31 -08:00
mem.c cxl/mem: Drop DVSEC vs EFI Memory Map sanity check 2022-04-12 19:11:57 -07:00
pci.c cxl/mbox: Use new return_code handling 2022-04-12 16:07:02 -07:00
pmem.c cxl/pmem: Remove CXL SET_PARTITION_INFO from exclusive_cmds list 2022-04-12 16:07:01 -07:00
port.c cxl/core/port: Add endpoint decoders 2022-02-08 22:57:32 -08:00