1633 lines
49 KiB
C
1633 lines
49 KiB
C
/*
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* Xilinx Axi Ethernet device driver
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*
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* Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
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* Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
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* Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
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* Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2010 - 2011 PetaLogix
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* Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
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*
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* This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
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* and Spartan6.
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*
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* TODO:
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* - Add Axi Fifo support.
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* - Factor out Axi DMA code into separate driver.
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* - Test and fix basic multicast filtering.
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* - Add support for extended multicast filtering.
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* - Test basic VLAN support.
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* - Add support for extended VLAN support.
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*/
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/phy.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include "xilinx_axienet.h"
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/* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
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#define TX_BD_NUM 64
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#define RX_BD_NUM 128
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/* Must be shorter than length of ethtool_drvinfo.driver field to fit */
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#define DRIVER_NAME "xaxienet"
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#define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
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#define DRIVER_VERSION "1.00a"
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#define AXIENET_REGS_N 32
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/* Match table for of_platform binding */
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static const struct of_device_id axienet_of_match[] = {
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{ .compatible = "xlnx,axi-ethernet-1.00.a", },
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{ .compatible = "xlnx,axi-ethernet-1.01.a", },
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{ .compatible = "xlnx,axi-ethernet-2.01.a", },
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{},
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};
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MODULE_DEVICE_TABLE(of, axienet_of_match);
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/* Option table for setting up Axi Ethernet hardware options */
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static struct axienet_option axienet_options[] = {
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/* Turn on jumbo packet support for both Rx and Tx */
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{
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.opt = XAE_OPTION_JUMBO,
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.reg = XAE_TC_OFFSET,
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.m_or = XAE_TC_JUM_MASK,
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}, {
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.opt = XAE_OPTION_JUMBO,
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.reg = XAE_RCW1_OFFSET,
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.m_or = XAE_RCW1_JUM_MASK,
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}, { /* Turn on VLAN packet support for both Rx and Tx */
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.opt = XAE_OPTION_VLAN,
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.reg = XAE_TC_OFFSET,
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.m_or = XAE_TC_VLAN_MASK,
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}, {
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.opt = XAE_OPTION_VLAN,
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.reg = XAE_RCW1_OFFSET,
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.m_or = XAE_RCW1_VLAN_MASK,
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}, { /* Turn on FCS stripping on receive packets */
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.opt = XAE_OPTION_FCS_STRIP,
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.reg = XAE_RCW1_OFFSET,
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.m_or = XAE_RCW1_FCS_MASK,
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}, { /* Turn on FCS insertion on transmit packets */
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.opt = XAE_OPTION_FCS_INSERT,
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.reg = XAE_TC_OFFSET,
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.m_or = XAE_TC_FCS_MASK,
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}, { /* Turn off length/type field checking on receive packets */
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.opt = XAE_OPTION_LENTYPE_ERR,
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.reg = XAE_RCW1_OFFSET,
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.m_or = XAE_RCW1_LT_DIS_MASK,
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}, { /* Turn on Rx flow control */
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.opt = XAE_OPTION_FLOW_CONTROL,
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.reg = XAE_FCC_OFFSET,
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.m_or = XAE_FCC_FCRX_MASK,
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}, { /* Turn on Tx flow control */
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.opt = XAE_OPTION_FLOW_CONTROL,
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.reg = XAE_FCC_OFFSET,
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.m_or = XAE_FCC_FCTX_MASK,
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}, { /* Turn on promiscuous frame filtering */
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.opt = XAE_OPTION_PROMISC,
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.reg = XAE_FMI_OFFSET,
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.m_or = XAE_FMI_PM_MASK,
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}, { /* Enable transmitter */
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.opt = XAE_OPTION_TXEN,
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.reg = XAE_TC_OFFSET,
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.m_or = XAE_TC_TX_MASK,
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}, { /* Enable receiver */
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.opt = XAE_OPTION_RXEN,
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.reg = XAE_RCW1_OFFSET,
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.m_or = XAE_RCW1_RX_MASK,
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},
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{}
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};
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/**
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* axienet_dma_in32 - Memory mapped Axi DMA register read
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* @lp: Pointer to axienet local structure
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* @reg: Address offset from the base address of the Axi DMA core
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*
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* Return: The contents of the Axi DMA register
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*
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* This function returns the contents of the corresponding Axi DMA register.
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*/
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static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
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{
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return in_be32(lp->dma_regs + reg);
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}
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/**
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* axienet_dma_out32 - Memory mapped Axi DMA register write.
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* @lp: Pointer to axienet local structure
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* @reg: Address offset from the base address of the Axi DMA core
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* @value: Value to be written into the Axi DMA register
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*
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* This function writes the desired value into the corresponding Axi DMA
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* register.
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*/
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static inline void axienet_dma_out32(struct axienet_local *lp,
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off_t reg, u32 value)
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{
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out_be32((lp->dma_regs + reg), value);
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}
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/**
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* axienet_dma_bd_release - Release buffer descriptor rings
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* @ndev: Pointer to the net_device structure
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*
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* This function is used to release the descriptors allocated in
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* axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
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* driver stop api is called.
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*/
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static void axienet_dma_bd_release(struct net_device *ndev)
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{
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int i;
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struct axienet_local *lp = netdev_priv(ndev);
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for (i = 0; i < RX_BD_NUM; i++) {
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dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
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lp->max_frm_size, DMA_FROM_DEVICE);
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dev_kfree_skb((struct sk_buff *)
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(lp->rx_bd_v[i].sw_id_offset));
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}
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if (lp->rx_bd_v) {
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dma_free_coherent(ndev->dev.parent,
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sizeof(*lp->rx_bd_v) * RX_BD_NUM,
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lp->rx_bd_v,
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lp->rx_bd_p);
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}
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if (lp->tx_bd_v) {
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dma_free_coherent(ndev->dev.parent,
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sizeof(*lp->tx_bd_v) * TX_BD_NUM,
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lp->tx_bd_v,
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lp->tx_bd_p);
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}
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}
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/**
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* axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
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* @ndev: Pointer to the net_device structure
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*
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* Return: 0, on success -ENOMEM, on failure
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*
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* This function is called to initialize the Rx and Tx DMA descriptor
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* rings. This initializes the descriptors with required default values
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* and is called when Axi Ethernet driver reset is called.
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*/
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static int axienet_dma_bd_init(struct net_device *ndev)
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{
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u32 cr;
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int i;
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struct sk_buff *skb;
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struct axienet_local *lp = netdev_priv(ndev);
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/* Reset the indexes which are used for accessing the BDs */
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lp->tx_bd_ci = 0;
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lp->tx_bd_tail = 0;
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lp->rx_bd_ci = 0;
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/* Allocate the Tx and Rx buffer descriptors. */
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lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
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sizeof(*lp->tx_bd_v) * TX_BD_NUM,
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&lp->tx_bd_p, GFP_KERNEL);
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if (!lp->tx_bd_v)
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goto out;
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lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
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sizeof(*lp->rx_bd_v) * RX_BD_NUM,
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&lp->rx_bd_p, GFP_KERNEL);
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if (!lp->rx_bd_v)
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goto out;
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for (i = 0; i < TX_BD_NUM; i++) {
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lp->tx_bd_v[i].next = lp->tx_bd_p +
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sizeof(*lp->tx_bd_v) *
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((i + 1) % TX_BD_NUM);
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}
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for (i = 0; i < RX_BD_NUM; i++) {
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lp->rx_bd_v[i].next = lp->rx_bd_p +
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sizeof(*lp->rx_bd_v) *
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((i + 1) % RX_BD_NUM);
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skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
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if (!skb)
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goto out;
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lp->rx_bd_v[i].sw_id_offset = (u32) skb;
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lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
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skb->data,
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lp->max_frm_size,
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DMA_FROM_DEVICE);
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lp->rx_bd_v[i].cntrl = lp->max_frm_size;
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}
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/* Start updating the Rx channel control register */
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cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
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/* Update the interrupt coalesce count */
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cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
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((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
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/* Update the delay timer count */
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cr = ((cr & ~XAXIDMA_DELAY_MASK) |
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(XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
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/* Enable coalesce, delay timer and error interrupts */
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cr |= XAXIDMA_IRQ_ALL_MASK;
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/* Write to the Rx channel control register */
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axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
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/* Start updating the Tx channel control register */
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cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
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/* Update the interrupt coalesce count */
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cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
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((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
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/* Update the delay timer count */
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cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
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(XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
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/* Enable coalesce, delay timer and error interrupts */
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cr |= XAXIDMA_IRQ_ALL_MASK;
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/* Write to the Tx channel control register */
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axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
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/* Populate the tail pointer and bring the Rx Axi DMA engine out of
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* halted state. This will make the Rx side ready for reception.
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*/
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axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
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cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
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axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
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cr | XAXIDMA_CR_RUNSTOP_MASK);
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axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
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(sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
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/* Write to the RS (Run-stop) bit in the Tx channel control register.
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* Tx channel is now ready to run. But only after we write to the
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* tail pointer register that the Tx channel will start transmitting.
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*/
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axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
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cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
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axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
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cr | XAXIDMA_CR_RUNSTOP_MASK);
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return 0;
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out:
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axienet_dma_bd_release(ndev);
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return -ENOMEM;
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}
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/**
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* axienet_set_mac_address - Write the MAC address
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* @ndev: Pointer to the net_device structure
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* @address: 6 byte Address to be written as MAC address
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*
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* This function is called to initialize the MAC address of the Axi Ethernet
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* core. It writes to the UAW0 and UAW1 registers of the core.
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*/
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static void axienet_set_mac_address(struct net_device *ndev,
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const void *address)
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{
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struct axienet_local *lp = netdev_priv(ndev);
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if (address)
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memcpy(ndev->dev_addr, address, ETH_ALEN);
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if (!is_valid_ether_addr(ndev->dev_addr))
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eth_hw_addr_random(ndev);
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/* Set up unicast MAC address filter set its mac address */
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axienet_iow(lp, XAE_UAW0_OFFSET,
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(ndev->dev_addr[0]) |
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(ndev->dev_addr[1] << 8) |
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(ndev->dev_addr[2] << 16) |
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(ndev->dev_addr[3] << 24));
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axienet_iow(lp, XAE_UAW1_OFFSET,
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(((axienet_ior(lp, XAE_UAW1_OFFSET)) &
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~XAE_UAW1_UNICASTADDR_MASK) |
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(ndev->dev_addr[4] |
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(ndev->dev_addr[5] << 8))));
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}
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/**
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* netdev_set_mac_address - Write the MAC address (from outside the driver)
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* @ndev: Pointer to the net_device structure
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* @p: 6 byte Address to be written as MAC address
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*
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* Return: 0 for all conditions. Presently, there is no failure case.
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*
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* This function is called to initialize the MAC address of the Axi Ethernet
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* core. It calls the core specific axienet_set_mac_address. This is the
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* function that goes into net_device_ops structure entry ndo_set_mac_address.
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*/
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static int netdev_set_mac_address(struct net_device *ndev, void *p)
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{
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struct sockaddr *addr = p;
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axienet_set_mac_address(ndev, addr->sa_data);
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return 0;
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}
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/**
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* axienet_set_multicast_list - Prepare the multicast table
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* @ndev: Pointer to the net_device structure
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*
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* This function is called to initialize the multicast table during
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* initialization. The Axi Ethernet basic multicast support has a four-entry
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* multicast table which is initialized here. Additionally this function
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* goes into the net_device_ops structure entry ndo_set_multicast_list. This
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* means whenever the multicast table entries need to be updated this
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* function gets called.
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*/
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static void axienet_set_multicast_list(struct net_device *ndev)
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{
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int i;
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u32 reg, af0reg, af1reg;
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struct axienet_local *lp = netdev_priv(ndev);
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if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
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netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
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/* We must make the kernel realize we had to move into
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* promiscuous mode. If it was a promiscuous mode request
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* the flag is already set. If not we set it.
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*/
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ndev->flags |= IFF_PROMISC;
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reg = axienet_ior(lp, XAE_FMI_OFFSET);
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reg |= XAE_FMI_PM_MASK;
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axienet_iow(lp, XAE_FMI_OFFSET, reg);
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dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
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} else if (!netdev_mc_empty(ndev)) {
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struct netdev_hw_addr *ha;
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i = 0;
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netdev_for_each_mc_addr(ha, ndev) {
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if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
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break;
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af0reg = (ha->addr[0]);
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af0reg |= (ha->addr[1] << 8);
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af0reg |= (ha->addr[2] << 16);
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af0reg |= (ha->addr[3] << 24);
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af1reg = (ha->addr[4]);
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af1reg |= (ha->addr[5] << 8);
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reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
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reg |= i;
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axienet_iow(lp, XAE_FMI_OFFSET, reg);
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axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
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axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
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i++;
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}
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} else {
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reg = axienet_ior(lp, XAE_FMI_OFFSET);
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reg &= ~XAE_FMI_PM_MASK;
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axienet_iow(lp, XAE_FMI_OFFSET, reg);
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for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
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reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
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reg |= i;
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axienet_iow(lp, XAE_FMI_OFFSET, reg);
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axienet_iow(lp, XAE_AF0_OFFSET, 0);
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axienet_iow(lp, XAE_AF1_OFFSET, 0);
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}
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dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
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}
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}
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|
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/**
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* axienet_setoptions - Set an Axi Ethernet option
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* @ndev: Pointer to the net_device structure
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* @options: Option to be enabled/disabled
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*
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* The Axi Ethernet core has multiple features which can be selectively turned
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* on or off. The typical options could be jumbo frame option, basic VLAN
|
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* option, promiscuous mode option etc. This function is used to set or clear
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* these options in the Axi Ethernet hardware. This is done through
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* axienet_option structure .
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*/
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static void axienet_setoptions(struct net_device *ndev, u32 options)
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{
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int reg;
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struct axienet_local *lp = netdev_priv(ndev);
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struct axienet_option *tp = &axienet_options[0];
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|
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while (tp->opt) {
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reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
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if (options & tp->opt)
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reg |= tp->m_or;
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axienet_iow(lp, tp->reg, reg);
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tp++;
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}
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lp->options |= options;
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}
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|
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static void __axienet_device_reset(struct axienet_local *lp, off_t offset)
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{
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u32 timeout;
|
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/* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
|
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* process of Axi DMA takes a while to complete as all pending
|
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* commands/transfers will be flushed or completed during this
|
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* reset process.
|
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*/
|
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axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
|
|
timeout = DELAY_OF_ONE_MILLISEC;
|
|
while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
|
|
udelay(1);
|
|
if (--timeout == 0) {
|
|
netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
|
|
__func__);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
|
|
* @ndev: Pointer to the net_device structure
|
|
*
|
|
* This function is called to reset and initialize the Axi Ethernet core. This
|
|
* is typically called during initialization. It does a reset of the Axi DMA
|
|
* Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
|
|
* areconnected to Axi Ethernet reset lines, this in turn resets the Axi
|
|
* Ethernet core. No separate hardware reset is done for the Axi Ethernet
|
|
* core.
|
|
*/
|
|
static void axienet_device_reset(struct net_device *ndev)
|
|
{
|
|
u32 axienet_status;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
__axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
|
|
__axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
|
|
|
|
lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
|
|
lp->options |= XAE_OPTION_VLAN;
|
|
lp->options &= (~XAE_OPTION_JUMBO);
|
|
|
|
if ((ndev->mtu > XAE_MTU) &&
|
|
(ndev->mtu <= XAE_JUMBO_MTU)) {
|
|
lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
|
|
XAE_TRL_SIZE;
|
|
|
|
if (lp->max_frm_size <= lp->rxmem)
|
|
lp->options |= XAE_OPTION_JUMBO;
|
|
}
|
|
|
|
if (axienet_dma_bd_init(ndev)) {
|
|
netdev_err(ndev, "%s: descriptor allocation failed\n",
|
|
__func__);
|
|
}
|
|
|
|
axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
|
|
axienet_status &= ~XAE_RCW1_RX_MASK;
|
|
axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
|
|
|
|
axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
|
|
if (axienet_status & XAE_INT_RXRJECT_MASK)
|
|
axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
|
|
|
|
axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
|
|
|
|
/* Sync default options with HW but leave receiver and
|
|
* transmitter disabled.
|
|
*/
|
|
axienet_setoptions(ndev, lp->options &
|
|
~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
|
|
axienet_set_mac_address(ndev, NULL);
|
|
axienet_set_multicast_list(ndev);
|
|
axienet_setoptions(ndev, lp->options);
|
|
|
|
netif_trans_update(ndev);
|
|
}
|
|
|
|
/**
|
|
* axienet_adjust_link - Adjust the PHY link speed/duplex.
|
|
* @ndev: Pointer to the net_device structure
|
|
*
|
|
* This function is called to change the speed and duplex setting after
|
|
* auto negotiation is done by the PHY. This is the function that gets
|
|
* registered with the PHY interface through the "of_phy_connect" call.
|
|
*/
|
|
static void axienet_adjust_link(struct net_device *ndev)
|
|
{
|
|
u32 emmc_reg;
|
|
u32 link_state;
|
|
u32 setspeed = 1;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
struct phy_device *phy = ndev->phydev;
|
|
|
|
link_state = phy->speed | (phy->duplex << 1) | phy->link;
|
|
if (lp->last_link != link_state) {
|
|
if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
|
|
if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X)
|
|
setspeed = 0;
|
|
} else {
|
|
if ((phy->speed == SPEED_1000) &&
|
|
(lp->phy_type == XAE_PHY_TYPE_MII))
|
|
setspeed = 0;
|
|
}
|
|
|
|
if (setspeed == 1) {
|
|
emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
|
|
emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
|
|
|
|
switch (phy->speed) {
|
|
case SPEED_1000:
|
|
emmc_reg |= XAE_EMMC_LINKSPD_1000;
|
|
break;
|
|
case SPEED_100:
|
|
emmc_reg |= XAE_EMMC_LINKSPD_100;
|
|
break;
|
|
case SPEED_10:
|
|
emmc_reg |= XAE_EMMC_LINKSPD_10;
|
|
break;
|
|
default:
|
|
dev_err(&ndev->dev, "Speed other than 10, 100 "
|
|
"or 1Gbps is not supported\n");
|
|
break;
|
|
}
|
|
|
|
axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
|
|
lp->last_link = link_state;
|
|
phy_print_status(phy);
|
|
} else {
|
|
netdev_err(ndev,
|
|
"Error setting Axi Ethernet mac speed\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* axienet_start_xmit_done - Invoked once a transmit is completed by the
|
|
* Axi DMA Tx channel.
|
|
* @ndev: Pointer to the net_device structure
|
|
*
|
|
* This function is invoked from the Axi DMA Tx isr to notify the completion
|
|
* of transmit operation. It clears fields in the corresponding Tx BDs and
|
|
* unmaps the corresponding buffer so that CPU can regain ownership of the
|
|
* buffer. It finally invokes "netif_wake_queue" to restart transmission if
|
|
* required.
|
|
*/
|
|
static void axienet_start_xmit_done(struct net_device *ndev)
|
|
{
|
|
u32 size = 0;
|
|
u32 packets = 0;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
struct axidma_bd *cur_p;
|
|
unsigned int status = 0;
|
|
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
|
|
status = cur_p->status;
|
|
while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
|
|
dma_unmap_single(ndev->dev.parent, cur_p->phys,
|
|
(cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
|
|
DMA_TO_DEVICE);
|
|
if (cur_p->app4)
|
|
dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
|
|
/*cur_p->phys = 0;*/
|
|
cur_p->app0 = 0;
|
|
cur_p->app1 = 0;
|
|
cur_p->app2 = 0;
|
|
cur_p->app4 = 0;
|
|
cur_p->status = 0;
|
|
|
|
size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
|
|
packets++;
|
|
|
|
++lp->tx_bd_ci;
|
|
lp->tx_bd_ci %= TX_BD_NUM;
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
|
|
status = cur_p->status;
|
|
}
|
|
|
|
ndev->stats.tx_packets += packets;
|
|
ndev->stats.tx_bytes += size;
|
|
netif_wake_queue(ndev);
|
|
}
|
|
|
|
/**
|
|
* axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
|
|
* @lp: Pointer to the axienet_local structure
|
|
* @num_frag: The number of BDs to check for
|
|
*
|
|
* Return: 0, on success
|
|
* NETDEV_TX_BUSY, if any of the descriptors are not free
|
|
*
|
|
* This function is invoked before BDs are allocated and transmission starts.
|
|
* This function returns 0 if a BD or group of BDs can be allocated for
|
|
* transmission. If the BD or any of the BDs are not free the function
|
|
* returns a busy status. This is invoked from axienet_start_xmit.
|
|
*/
|
|
static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
|
|
int num_frag)
|
|
{
|
|
struct axidma_bd *cur_p;
|
|
cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
|
|
if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
|
|
return NETDEV_TX_BUSY;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* axienet_start_xmit - Starts the transmission.
|
|
* @skb: sk_buff pointer that contains data to be Txed.
|
|
* @ndev: Pointer to net_device structure.
|
|
*
|
|
* Return: NETDEV_TX_OK, on success
|
|
* NETDEV_TX_BUSY, if any of the descriptors are not free
|
|
*
|
|
* This function is invoked from upper layers to initiate transmission. The
|
|
* function uses the next available free BDs and populates their fields to
|
|
* start the transmission. Additionally if checksum offloading is supported,
|
|
* it populates AXI Stream Control fields with appropriate values.
|
|
*/
|
|
static int axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
|
|
{
|
|
u32 ii;
|
|
u32 num_frag;
|
|
u32 csum_start_off;
|
|
u32 csum_index_off;
|
|
skb_frag_t *frag;
|
|
dma_addr_t tail_p;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
struct axidma_bd *cur_p;
|
|
|
|
num_frag = skb_shinfo(skb)->nr_frags;
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
|
|
|
|
if (axienet_check_tx_bd_space(lp, num_frag)) {
|
|
if (!netif_queue_stopped(ndev))
|
|
netif_stop_queue(ndev);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
if (skb->ip_summed == CHECKSUM_PARTIAL) {
|
|
if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
|
|
/* Tx Full Checksum Offload Enabled */
|
|
cur_p->app0 |= 2;
|
|
} else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
|
|
csum_start_off = skb_transport_offset(skb);
|
|
csum_index_off = csum_start_off + skb->csum_offset;
|
|
/* Tx Partial Checksum Offload Enabled */
|
|
cur_p->app0 |= 1;
|
|
cur_p->app1 = (csum_start_off << 16) | csum_index_off;
|
|
}
|
|
} else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
|
|
cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
|
|
}
|
|
|
|
cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
|
|
cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
|
|
skb_headlen(skb), DMA_TO_DEVICE);
|
|
|
|
for (ii = 0; ii < num_frag; ii++) {
|
|
++lp->tx_bd_tail;
|
|
lp->tx_bd_tail %= TX_BD_NUM;
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
|
|
frag = &skb_shinfo(skb)->frags[ii];
|
|
cur_p->phys = dma_map_single(ndev->dev.parent,
|
|
skb_frag_address(frag),
|
|
skb_frag_size(frag),
|
|
DMA_TO_DEVICE);
|
|
cur_p->cntrl = skb_frag_size(frag);
|
|
}
|
|
|
|
cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
|
|
cur_p->app4 = (unsigned long)skb;
|
|
|
|
tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
|
|
/* Start the transfer */
|
|
axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
|
|
++lp->tx_bd_tail;
|
|
lp->tx_bd_tail %= TX_BD_NUM;
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
/**
|
|
* axienet_recv - Is called from Axi DMA Rx Isr to complete the received
|
|
* BD processing.
|
|
* @ndev: Pointer to net_device structure.
|
|
*
|
|
* This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
|
|
* does minimal processing and invokes "netif_rx" to complete further
|
|
* processing.
|
|
*/
|
|
static void axienet_recv(struct net_device *ndev)
|
|
{
|
|
u32 length;
|
|
u32 csumstatus;
|
|
u32 size = 0;
|
|
u32 packets = 0;
|
|
dma_addr_t tail_p = 0;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
struct sk_buff *skb, *new_skb;
|
|
struct axidma_bd *cur_p;
|
|
|
|
cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
|
|
|
|
while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
|
|
tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
|
|
skb = (struct sk_buff *) (cur_p->sw_id_offset);
|
|
length = cur_p->app4 & 0x0000FFFF;
|
|
|
|
dma_unmap_single(ndev->dev.parent, cur_p->phys,
|
|
lp->max_frm_size,
|
|
DMA_FROM_DEVICE);
|
|
|
|
skb_put(skb, length);
|
|
skb->protocol = eth_type_trans(skb, ndev);
|
|
/*skb_checksum_none_assert(skb);*/
|
|
skb->ip_summed = CHECKSUM_NONE;
|
|
|
|
/* if we're doing Rx csum offload, set it up */
|
|
if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
|
|
csumstatus = (cur_p->app2 &
|
|
XAE_FULL_CSUM_STATUS_MASK) >> 3;
|
|
if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
|
|
(csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
|
|
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
|
}
|
|
} else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
|
|
skb->protocol == htons(ETH_P_IP) &&
|
|
skb->len > 64) {
|
|
skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
|
|
skb->ip_summed = CHECKSUM_COMPLETE;
|
|
}
|
|
|
|
netif_rx(skb);
|
|
|
|
size += length;
|
|
packets++;
|
|
|
|
new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
|
|
if (!new_skb)
|
|
return;
|
|
|
|
cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
|
|
lp->max_frm_size,
|
|
DMA_FROM_DEVICE);
|
|
cur_p->cntrl = lp->max_frm_size;
|
|
cur_p->status = 0;
|
|
cur_p->sw_id_offset = (u32) new_skb;
|
|
|
|
++lp->rx_bd_ci;
|
|
lp->rx_bd_ci %= RX_BD_NUM;
|
|
cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
|
|
}
|
|
|
|
ndev->stats.rx_packets += packets;
|
|
ndev->stats.rx_bytes += size;
|
|
|
|
if (tail_p)
|
|
axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
|
|
}
|
|
|
|
/**
|
|
* axienet_tx_irq - Tx Done Isr.
|
|
* @irq: irq number
|
|
* @_ndev: net_device pointer
|
|
*
|
|
* Return: IRQ_HANDLED for all cases.
|
|
*
|
|
* This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
|
|
* to complete the BD processing.
|
|
*/
|
|
static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
|
|
{
|
|
u32 cr;
|
|
unsigned int status;
|
|
struct net_device *ndev = _ndev;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
|
|
if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
|
|
axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
|
|
axienet_start_xmit_done(lp->ndev);
|
|
goto out;
|
|
}
|
|
if (!(status & XAXIDMA_IRQ_ALL_MASK))
|
|
dev_err(&ndev->dev, "No interrupts asserted in Tx path\n");
|
|
if (status & XAXIDMA_IRQ_ERROR_MASK) {
|
|
dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
|
|
dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
|
|
(lp->tx_bd_v[lp->tx_bd_ci]).phys);
|
|
|
|
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
|
|
/* Disable coalesce, delay timer and error interrupts */
|
|
cr &= (~XAXIDMA_IRQ_ALL_MASK);
|
|
/* Write to the Tx channel control register */
|
|
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
|
|
|
|
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
|
|
/* Disable coalesce, delay timer and error interrupts */
|
|
cr &= (~XAXIDMA_IRQ_ALL_MASK);
|
|
/* Write to the Rx channel control register */
|
|
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
|
|
|
|
tasklet_schedule(&lp->dma_err_tasklet);
|
|
axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
|
|
}
|
|
out:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* axienet_rx_irq - Rx Isr.
|
|
* @irq: irq number
|
|
* @_ndev: net_device pointer
|
|
*
|
|
* Return: IRQ_HANDLED for all cases.
|
|
*
|
|
* This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
|
|
* processing.
|
|
*/
|
|
static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
|
|
{
|
|
u32 cr;
|
|
unsigned int status;
|
|
struct net_device *ndev = _ndev;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
|
|
if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
|
|
axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
|
|
axienet_recv(lp->ndev);
|
|
goto out;
|
|
}
|
|
if (!(status & XAXIDMA_IRQ_ALL_MASK))
|
|
dev_err(&ndev->dev, "No interrupts asserted in Rx path\n");
|
|
if (status & XAXIDMA_IRQ_ERROR_MASK) {
|
|
dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
|
|
dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
|
|
(lp->rx_bd_v[lp->rx_bd_ci]).phys);
|
|
|
|
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
|
|
/* Disable coalesce, delay timer and error interrupts */
|
|
cr &= (~XAXIDMA_IRQ_ALL_MASK);
|
|
/* Finally write to the Tx channel control register */
|
|
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
|
|
|
|
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
|
|
/* Disable coalesce, delay timer and error interrupts */
|
|
cr &= (~XAXIDMA_IRQ_ALL_MASK);
|
|
/* write to the Rx channel control register */
|
|
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
|
|
|
|
tasklet_schedule(&lp->dma_err_tasklet);
|
|
axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
|
|
}
|
|
out:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void axienet_dma_err_handler(unsigned long data);
|
|
|
|
/**
|
|
* axienet_open - Driver open routine.
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* Return: 0, on success.
|
|
* -ENODEV, if PHY cannot be connected to
|
|
* non-zero error value on failure
|
|
*
|
|
* This is the driver open routine. It calls phy_start to start the PHY device.
|
|
* It also allocates interrupt service routines, enables the interrupt lines
|
|
* and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
|
|
* descriptors are initialized.
|
|
*/
|
|
static int axienet_open(struct net_device *ndev)
|
|
{
|
|
int ret, mdio_mcreg;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
struct phy_device *phydev = NULL;
|
|
|
|
dev_dbg(&ndev->dev, "axienet_open()\n");
|
|
|
|
mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
|
|
ret = axienet_mdio_wait_until_ready(lp);
|
|
if (ret < 0)
|
|
return ret;
|
|
/* Disable the MDIO interface till Axi Ethernet Reset is completed.
|
|
* When we do an Axi Ethernet reset, it resets the complete core
|
|
* including the MDIO. If MDIO is not disabled when the reset
|
|
* process is started, MDIO will be broken afterwards.
|
|
*/
|
|
axienet_iow(lp, XAE_MDIO_MC_OFFSET,
|
|
(mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
|
|
axienet_device_reset(ndev);
|
|
/* Enable the MDIO */
|
|
axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
|
|
ret = axienet_mdio_wait_until_ready(lp);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (lp->phy_node) {
|
|
if (lp->phy_type == XAE_PHY_TYPE_GMII) {
|
|
phydev = of_phy_connect(lp->ndev, lp->phy_node,
|
|
axienet_adjust_link, 0,
|
|
PHY_INTERFACE_MODE_GMII);
|
|
} else if (lp->phy_type == XAE_PHY_TYPE_RGMII_2_0) {
|
|
phydev = of_phy_connect(lp->ndev, lp->phy_node,
|
|
axienet_adjust_link, 0,
|
|
PHY_INTERFACE_MODE_RGMII_ID);
|
|
}
|
|
|
|
if (!phydev)
|
|
dev_err(lp->dev, "of_phy_connect() failed\n");
|
|
else
|
|
phy_start(phydev);
|
|
}
|
|
|
|
/* Enable tasklets for Axi DMA error handling */
|
|
tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
|
|
(unsigned long) lp);
|
|
|
|
/* Enable interrupts for Axi DMA Tx */
|
|
ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
|
|
if (ret)
|
|
goto err_tx_irq;
|
|
/* Enable interrupts for Axi DMA Rx */
|
|
ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
|
|
if (ret)
|
|
goto err_rx_irq;
|
|
|
|
return 0;
|
|
|
|
err_rx_irq:
|
|
free_irq(lp->tx_irq, ndev);
|
|
err_tx_irq:
|
|
if (phydev)
|
|
phy_disconnect(phydev);
|
|
tasklet_kill(&lp->dma_err_tasklet);
|
|
dev_err(lp->dev, "request_irq() failed\n");
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* axienet_stop - Driver stop routine.
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* Return: 0, on success.
|
|
*
|
|
* This is the driver stop routine. It calls phy_disconnect to stop the PHY
|
|
* device. It also removes the interrupt handlers and disables the interrupts.
|
|
* The Axi DMA Tx/Rx BDs are released.
|
|
*/
|
|
static int axienet_stop(struct net_device *ndev)
|
|
{
|
|
u32 cr;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
dev_dbg(&ndev->dev, "axienet_close()\n");
|
|
|
|
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
|
|
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
|
|
cr & (~XAXIDMA_CR_RUNSTOP_MASK));
|
|
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
|
|
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
|
|
cr & (~XAXIDMA_CR_RUNSTOP_MASK));
|
|
axienet_setoptions(ndev, lp->options &
|
|
~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
|
|
|
|
tasklet_kill(&lp->dma_err_tasklet);
|
|
|
|
free_irq(lp->tx_irq, ndev);
|
|
free_irq(lp->rx_irq, ndev);
|
|
|
|
if (ndev->phydev)
|
|
phy_disconnect(ndev->phydev);
|
|
|
|
axienet_dma_bd_release(ndev);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* axienet_change_mtu - Driver change mtu routine.
|
|
* @ndev: Pointer to net_device structure
|
|
* @new_mtu: New mtu value to be applied
|
|
*
|
|
* Return: Always returns 0 (success).
|
|
*
|
|
* This is the change mtu driver routine. It checks if the Axi Ethernet
|
|
* hardware supports jumbo frames before changing the mtu. This can be
|
|
* called only when the device is not up.
|
|
*/
|
|
static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
|
|
{
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
if (netif_running(ndev))
|
|
return -EBUSY;
|
|
|
|
if ((new_mtu + VLAN_ETH_HLEN +
|
|
XAE_TRL_SIZE) > lp->rxmem)
|
|
return -EINVAL;
|
|
|
|
ndev->mtu = new_mtu;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
/**
|
|
* axienet_poll_controller - Axi Ethernet poll mechanism.
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
|
|
* to polling the ISRs and are enabled back after the polling is done.
|
|
*/
|
|
static void axienet_poll_controller(struct net_device *ndev)
|
|
{
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
disable_irq(lp->tx_irq);
|
|
disable_irq(lp->rx_irq);
|
|
axienet_rx_irq(lp->tx_irq, ndev);
|
|
axienet_tx_irq(lp->rx_irq, ndev);
|
|
enable_irq(lp->tx_irq);
|
|
enable_irq(lp->rx_irq);
|
|
}
|
|
#endif
|
|
|
|
static const struct net_device_ops axienet_netdev_ops = {
|
|
.ndo_open = axienet_open,
|
|
.ndo_stop = axienet_stop,
|
|
.ndo_start_xmit = axienet_start_xmit,
|
|
.ndo_change_mtu = axienet_change_mtu,
|
|
.ndo_set_mac_address = netdev_set_mac_address,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_set_rx_mode = axienet_set_multicast_list,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = axienet_poll_controller,
|
|
#endif
|
|
};
|
|
|
|
/**
|
|
* axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
|
|
* @ndev: Pointer to net_device structure
|
|
* @ed: Pointer to ethtool_drvinfo structure
|
|
*
|
|
* This implements ethtool command for getting the driver information.
|
|
* Issue "ethtool -i ethX" under linux prompt to execute this function.
|
|
*/
|
|
static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
|
|
struct ethtool_drvinfo *ed)
|
|
{
|
|
strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
|
|
strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
|
|
}
|
|
|
|
/**
|
|
* axienet_ethtools_get_regs_len - Get the total regs length present in the
|
|
* AxiEthernet core.
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* This implements ethtool command for getting the total register length
|
|
* information.
|
|
*
|
|
* Return: the total regs length
|
|
*/
|
|
static int axienet_ethtools_get_regs_len(struct net_device *ndev)
|
|
{
|
|
return sizeof(u32) * AXIENET_REGS_N;
|
|
}
|
|
|
|
/**
|
|
* axienet_ethtools_get_regs - Dump the contents of all registers present
|
|
* in AxiEthernet core.
|
|
* @ndev: Pointer to net_device structure
|
|
* @regs: Pointer to ethtool_regs structure
|
|
* @ret: Void pointer used to return the contents of the registers.
|
|
*
|
|
* This implements ethtool command for getting the Axi Ethernet register dump.
|
|
* Issue "ethtool -d ethX" to execute this function.
|
|
*/
|
|
static void axienet_ethtools_get_regs(struct net_device *ndev,
|
|
struct ethtool_regs *regs, void *ret)
|
|
{
|
|
u32 *data = (u32 *) ret;
|
|
size_t len = sizeof(u32) * AXIENET_REGS_N;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
regs->version = 0;
|
|
regs->len = len;
|
|
|
|
memset(data, 0, len);
|
|
data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
|
|
data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
|
|
data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
|
|
data[3] = axienet_ior(lp, XAE_IS_OFFSET);
|
|
data[4] = axienet_ior(lp, XAE_IP_OFFSET);
|
|
data[5] = axienet_ior(lp, XAE_IE_OFFSET);
|
|
data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
|
|
data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
|
|
data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
|
|
data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
|
|
data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
|
|
data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
|
|
data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
|
|
data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
|
|
data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
|
|
data[15] = axienet_ior(lp, XAE_TC_OFFSET);
|
|
data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
|
|
data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
|
|
data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
|
|
data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
|
|
data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
|
|
data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
|
|
data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
|
|
data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
|
|
data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
|
|
data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
|
|
data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
|
|
data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
|
|
data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
|
|
data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
|
|
data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
|
|
data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
|
|
}
|
|
|
|
/**
|
|
* axienet_ethtools_get_pauseparam - Get the pause parameter setting for
|
|
* Tx and Rx paths.
|
|
* @ndev: Pointer to net_device structure
|
|
* @epauseparm: Pointer to ethtool_pauseparam structure.
|
|
*
|
|
* This implements ethtool command for getting axi ethernet pause frame
|
|
* setting. Issue "ethtool -a ethX" to execute this function.
|
|
*/
|
|
static void
|
|
axienet_ethtools_get_pauseparam(struct net_device *ndev,
|
|
struct ethtool_pauseparam *epauseparm)
|
|
{
|
|
u32 regval;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
epauseparm->autoneg = 0;
|
|
regval = axienet_ior(lp, XAE_FCC_OFFSET);
|
|
epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
|
|
epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
|
|
}
|
|
|
|
/**
|
|
* axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
|
|
* settings.
|
|
* @ndev: Pointer to net_device structure
|
|
* @epauseparm:Pointer to ethtool_pauseparam structure
|
|
*
|
|
* This implements ethtool command for enabling flow control on Rx and Tx
|
|
* paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
|
|
* function.
|
|
*
|
|
* Return: 0 on success, -EFAULT if device is running
|
|
*/
|
|
static int
|
|
axienet_ethtools_set_pauseparam(struct net_device *ndev,
|
|
struct ethtool_pauseparam *epauseparm)
|
|
{
|
|
u32 regval = 0;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
if (netif_running(ndev)) {
|
|
netdev_err(ndev,
|
|
"Please stop netif before applying configuration\n");
|
|
return -EFAULT;
|
|
}
|
|
|
|
regval = axienet_ior(lp, XAE_FCC_OFFSET);
|
|
if (epauseparm->tx_pause)
|
|
regval |= XAE_FCC_FCTX_MASK;
|
|
else
|
|
regval &= ~XAE_FCC_FCTX_MASK;
|
|
if (epauseparm->rx_pause)
|
|
regval |= XAE_FCC_FCRX_MASK;
|
|
else
|
|
regval &= ~XAE_FCC_FCRX_MASK;
|
|
axienet_iow(lp, XAE_FCC_OFFSET, regval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
|
|
* @ndev: Pointer to net_device structure
|
|
* @ecoalesce: Pointer to ethtool_coalesce structure
|
|
*
|
|
* This implements ethtool command for getting the DMA interrupt coalescing
|
|
* count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
|
|
* execute this function.
|
|
*
|
|
* Return: 0 always
|
|
*/
|
|
static int axienet_ethtools_get_coalesce(struct net_device *ndev,
|
|
struct ethtool_coalesce *ecoalesce)
|
|
{
|
|
u32 regval = 0;
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
|
|
ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
|
|
>> XAXIDMA_COALESCE_SHIFT;
|
|
regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
|
|
ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
|
|
>> XAXIDMA_COALESCE_SHIFT;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
|
|
* @ndev: Pointer to net_device structure
|
|
* @ecoalesce: Pointer to ethtool_coalesce structure
|
|
*
|
|
* This implements ethtool command for setting the DMA interrupt coalescing
|
|
* count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
|
|
* prompt to execute this function.
|
|
*
|
|
* Return: 0, on success, Non-zero error value on failure.
|
|
*/
|
|
static int axienet_ethtools_set_coalesce(struct net_device *ndev,
|
|
struct ethtool_coalesce *ecoalesce)
|
|
{
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
if (netif_running(ndev)) {
|
|
netdev_err(ndev,
|
|
"Please stop netif before applying configuration\n");
|
|
return -EFAULT;
|
|
}
|
|
|
|
if ((ecoalesce->rx_coalesce_usecs) ||
|
|
(ecoalesce->rx_coalesce_usecs_irq) ||
|
|
(ecoalesce->rx_max_coalesced_frames_irq) ||
|
|
(ecoalesce->tx_coalesce_usecs) ||
|
|
(ecoalesce->tx_coalesce_usecs_irq) ||
|
|
(ecoalesce->tx_max_coalesced_frames_irq) ||
|
|
(ecoalesce->stats_block_coalesce_usecs) ||
|
|
(ecoalesce->use_adaptive_rx_coalesce) ||
|
|
(ecoalesce->use_adaptive_tx_coalesce) ||
|
|
(ecoalesce->pkt_rate_low) ||
|
|
(ecoalesce->rx_coalesce_usecs_low) ||
|
|
(ecoalesce->rx_max_coalesced_frames_low) ||
|
|
(ecoalesce->tx_coalesce_usecs_low) ||
|
|
(ecoalesce->tx_max_coalesced_frames_low) ||
|
|
(ecoalesce->pkt_rate_high) ||
|
|
(ecoalesce->rx_coalesce_usecs_high) ||
|
|
(ecoalesce->rx_max_coalesced_frames_high) ||
|
|
(ecoalesce->tx_coalesce_usecs_high) ||
|
|
(ecoalesce->tx_max_coalesced_frames_high) ||
|
|
(ecoalesce->rate_sample_interval))
|
|
return -EOPNOTSUPP;
|
|
if (ecoalesce->rx_max_coalesced_frames)
|
|
lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
|
|
if (ecoalesce->tx_max_coalesced_frames)
|
|
lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ethtool_ops axienet_ethtool_ops = {
|
|
.get_drvinfo = axienet_ethtools_get_drvinfo,
|
|
.get_regs_len = axienet_ethtools_get_regs_len,
|
|
.get_regs = axienet_ethtools_get_regs,
|
|
.get_link = ethtool_op_get_link,
|
|
.get_pauseparam = axienet_ethtools_get_pauseparam,
|
|
.set_pauseparam = axienet_ethtools_set_pauseparam,
|
|
.get_coalesce = axienet_ethtools_get_coalesce,
|
|
.set_coalesce = axienet_ethtools_set_coalesce,
|
|
.get_link_ksettings = phy_ethtool_get_link_ksettings,
|
|
.set_link_ksettings = phy_ethtool_set_link_ksettings,
|
|
};
|
|
|
|
/**
|
|
* axienet_dma_err_handler - Tasklet handler for Axi DMA Error
|
|
* @data: Data passed
|
|
*
|
|
* Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
|
|
* Tx/Rx BDs.
|
|
*/
|
|
static void axienet_dma_err_handler(unsigned long data)
|
|
{
|
|
u32 axienet_status;
|
|
u32 cr, i;
|
|
int mdio_mcreg;
|
|
struct axienet_local *lp = (struct axienet_local *) data;
|
|
struct net_device *ndev = lp->ndev;
|
|
struct axidma_bd *cur_p;
|
|
|
|
axienet_setoptions(ndev, lp->options &
|
|
~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
|
|
mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
|
|
axienet_mdio_wait_until_ready(lp);
|
|
/* Disable the MDIO interface till Axi Ethernet Reset is completed.
|
|
* When we do an Axi Ethernet reset, it resets the complete core
|
|
* including the MDIO. So if MDIO is not disabled when the reset
|
|
* process is started, MDIO will be broken afterwards.
|
|
*/
|
|
axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
|
|
~XAE_MDIO_MC_MDIOEN_MASK));
|
|
|
|
__axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
|
|
__axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
|
|
|
|
axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
|
|
axienet_mdio_wait_until_ready(lp);
|
|
|
|
for (i = 0; i < TX_BD_NUM; i++) {
|
|
cur_p = &lp->tx_bd_v[i];
|
|
if (cur_p->phys)
|
|
dma_unmap_single(ndev->dev.parent, cur_p->phys,
|
|
(cur_p->cntrl &
|
|
XAXIDMA_BD_CTRL_LENGTH_MASK),
|
|
DMA_TO_DEVICE);
|
|
if (cur_p->app4)
|
|
dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
|
|
cur_p->phys = 0;
|
|
cur_p->cntrl = 0;
|
|
cur_p->status = 0;
|
|
cur_p->app0 = 0;
|
|
cur_p->app1 = 0;
|
|
cur_p->app2 = 0;
|
|
cur_p->app3 = 0;
|
|
cur_p->app4 = 0;
|
|
cur_p->sw_id_offset = 0;
|
|
}
|
|
|
|
for (i = 0; i < RX_BD_NUM; i++) {
|
|
cur_p = &lp->rx_bd_v[i];
|
|
cur_p->status = 0;
|
|
cur_p->app0 = 0;
|
|
cur_p->app1 = 0;
|
|
cur_p->app2 = 0;
|
|
cur_p->app3 = 0;
|
|
cur_p->app4 = 0;
|
|
}
|
|
|
|
lp->tx_bd_ci = 0;
|
|
lp->tx_bd_tail = 0;
|
|
lp->rx_bd_ci = 0;
|
|
|
|
/* Start updating the Rx channel control register */
|
|
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
|
|
/* Update the interrupt coalesce count */
|
|
cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
|
|
(XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
|
|
/* Update the delay timer count */
|
|
cr = ((cr & ~XAXIDMA_DELAY_MASK) |
|
|
(XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
|
|
/* Enable coalesce, delay timer and error interrupts */
|
|
cr |= XAXIDMA_IRQ_ALL_MASK;
|
|
/* Finally write to the Rx channel control register */
|
|
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
|
|
|
|
/* Start updating the Tx channel control register */
|
|
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
|
|
/* Update the interrupt coalesce count */
|
|
cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
|
|
(XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
|
|
/* Update the delay timer count */
|
|
cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
|
|
(XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
|
|
/* Enable coalesce, delay timer and error interrupts */
|
|
cr |= XAXIDMA_IRQ_ALL_MASK;
|
|
/* Finally write to the Tx channel control register */
|
|
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
|
|
|
|
/* Populate the tail pointer and bring the Rx Axi DMA engine out of
|
|
* halted state. This will make the Rx side ready for reception.
|
|
*/
|
|
axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
|
|
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
|
|
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
|
|
cr | XAXIDMA_CR_RUNSTOP_MASK);
|
|
axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
|
|
(sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
|
|
|
|
/* Write to the RS (Run-stop) bit in the Tx channel control register.
|
|
* Tx channel is now ready to run. But only after we write to the
|
|
* tail pointer register that the Tx channel will start transmitting
|
|
*/
|
|
axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
|
|
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
|
|
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
|
|
cr | XAXIDMA_CR_RUNSTOP_MASK);
|
|
|
|
axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
|
|
axienet_status &= ~XAE_RCW1_RX_MASK;
|
|
axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
|
|
|
|
axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
|
|
if (axienet_status & XAE_INT_RXRJECT_MASK)
|
|
axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
|
|
axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
|
|
|
|
/* Sync default options with HW but leave receiver and
|
|
* transmitter disabled.
|
|
*/
|
|
axienet_setoptions(ndev, lp->options &
|
|
~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
|
|
axienet_set_mac_address(ndev, NULL);
|
|
axienet_set_multicast_list(ndev);
|
|
axienet_setoptions(ndev, lp->options);
|
|
}
|
|
|
|
/**
|
|
* axienet_probe - Axi Ethernet probe function.
|
|
* @pdev: Pointer to platform device structure.
|
|
*
|
|
* Return: 0, on success
|
|
* Non-zero error value on failure.
|
|
*
|
|
* This is the probe routine for Axi Ethernet driver. This is called before
|
|
* any other driver routines are invoked. It allocates and sets up the Ethernet
|
|
* device. Parses through device tree and populates fields of
|
|
* axienet_local. It registers the Ethernet device.
|
|
*/
|
|
static int axienet_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct device_node *np;
|
|
struct axienet_local *lp;
|
|
struct net_device *ndev;
|
|
const void *mac_addr;
|
|
struct resource *ethres, dmares;
|
|
u32 value;
|
|
|
|
ndev = alloc_etherdev(sizeof(*lp));
|
|
if (!ndev)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, ndev);
|
|
|
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
|
|
ndev->features = NETIF_F_SG;
|
|
ndev->netdev_ops = &axienet_netdev_ops;
|
|
ndev->ethtool_ops = &axienet_ethtool_ops;
|
|
|
|
/* MTU range: 64 - 9000 */
|
|
ndev->min_mtu = 64;
|
|
ndev->max_mtu = XAE_JUMBO_MTU;
|
|
|
|
lp = netdev_priv(ndev);
|
|
lp->ndev = ndev;
|
|
lp->dev = &pdev->dev;
|
|
lp->options = XAE_OPTION_DEFAULTS;
|
|
/* Map device registers */
|
|
ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
|
|
if (IS_ERR(lp->regs)) {
|
|
dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n");
|
|
ret = PTR_ERR(lp->regs);
|
|
goto free_netdev;
|
|
}
|
|
|
|
/* Setup checksum offload, but default to off if not specified */
|
|
lp->features = 0;
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
|
|
if (!ret) {
|
|
switch (value) {
|
|
case 1:
|
|
lp->csum_offload_on_tx_path =
|
|
XAE_FEATURE_PARTIAL_TX_CSUM;
|
|
lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
|
|
/* Can checksum TCP/UDP over IPv4. */
|
|
ndev->features |= NETIF_F_IP_CSUM;
|
|
break;
|
|
case 2:
|
|
lp->csum_offload_on_tx_path =
|
|
XAE_FEATURE_FULL_TX_CSUM;
|
|
lp->features |= XAE_FEATURE_FULL_TX_CSUM;
|
|
/* Can checksum TCP/UDP over IPv4. */
|
|
ndev->features |= NETIF_F_IP_CSUM;
|
|
break;
|
|
default:
|
|
lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
|
|
}
|
|
}
|
|
ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
|
|
if (!ret) {
|
|
switch (value) {
|
|
case 1:
|
|
lp->csum_offload_on_rx_path =
|
|
XAE_FEATURE_PARTIAL_RX_CSUM;
|
|
lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
|
|
break;
|
|
case 2:
|
|
lp->csum_offload_on_rx_path =
|
|
XAE_FEATURE_FULL_RX_CSUM;
|
|
lp->features |= XAE_FEATURE_FULL_RX_CSUM;
|
|
break;
|
|
default:
|
|
lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
|
|
}
|
|
}
|
|
/* For supporting jumbo frames, the Axi Ethernet hardware must have
|
|
* a larger Rx/Tx Memory. Typically, the size must be large so that
|
|
* we can enable jumbo option and start supporting jumbo frames.
|
|
* Here we check for memory allocated for Rx/Tx in the hardware from
|
|
* the device-tree and accordingly set flags.
|
|
*/
|
|
of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
|
|
of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type);
|
|
|
|
/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
|
|
np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
|
|
if (!np) {
|
|
dev_err(&pdev->dev, "could not find DMA node\n");
|
|
ret = -ENODEV;
|
|
goto free_netdev;
|
|
}
|
|
ret = of_address_to_resource(np, 0, &dmares);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to get DMA resource\n");
|
|
goto free_netdev;
|
|
}
|
|
lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares);
|
|
if (IS_ERR(lp->dma_regs)) {
|
|
dev_err(&pdev->dev, "could not map DMA regs\n");
|
|
ret = PTR_ERR(lp->dma_regs);
|
|
goto free_netdev;
|
|
}
|
|
lp->rx_irq = irq_of_parse_and_map(np, 1);
|
|
lp->tx_irq = irq_of_parse_and_map(np, 0);
|
|
of_node_put(np);
|
|
if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
|
|
dev_err(&pdev->dev, "could not determine irqs\n");
|
|
ret = -ENOMEM;
|
|
goto free_netdev;
|
|
}
|
|
|
|
/* Retrieve the MAC address */
|
|
mac_addr = of_get_mac_address(pdev->dev.of_node);
|
|
if (!mac_addr) {
|
|
dev_err(&pdev->dev, "could not find MAC address\n");
|
|
goto free_netdev;
|
|
}
|
|
axienet_set_mac_address(ndev, mac_addr);
|
|
|
|
lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
|
|
lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
|
|
|
|
lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
|
|
if (lp->phy_node) {
|
|
ret = axienet_mdio_setup(lp, pdev->dev.of_node);
|
|
if (ret)
|
|
dev_warn(&pdev->dev, "error registering MDIO bus\n");
|
|
}
|
|
|
|
ret = register_netdev(lp->ndev);
|
|
if (ret) {
|
|
dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
|
|
goto free_netdev;
|
|
}
|
|
|
|
return 0;
|
|
|
|
free_netdev:
|
|
free_netdev(ndev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int axienet_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
struct axienet_local *lp = netdev_priv(ndev);
|
|
|
|
axienet_mdio_teardown(lp);
|
|
unregister_netdev(ndev);
|
|
|
|
of_node_put(lp->phy_node);
|
|
lp->phy_node = NULL;
|
|
|
|
free_netdev(ndev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver axienet_driver = {
|
|
.probe = axienet_probe,
|
|
.remove = axienet_remove,
|
|
.driver = {
|
|
.name = "xilinx_axienet",
|
|
.of_match_table = axienet_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(axienet_driver);
|
|
|
|
MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
|
|
MODULE_AUTHOR("Xilinx");
|
|
MODULE_LICENSE("GPL");
|