Vineet Gupta 795f455856 ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency) ... L2 cache on ARCHS processors is called SLC (System Level Cache) For working DMA (in absence of hardware assisted IO Coherency) we need to manage SLC explicitly when buffers transition between cpu and controllers. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-25 06:00:19 +05:30
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asm	ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)	2015-06-25 06:00:19 +05:30
uapi/asm	ARC: mm: document system mem map clearly	2015-06-19 18:09:29 +05:30