450 lines
12 KiB
C
450 lines
12 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <linux/jump_label.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#include <asm/fpsimd.h>
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static bool __hyp_text __fpsimd_enabled_nvhe(void)
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{
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return !(read_sysreg(cptr_el2) & CPTR_EL2_TFP);
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}
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static bool __hyp_text __fpsimd_enabled_vhe(void)
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{
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return !!(read_sysreg(cpacr_el1) & CPACR_EL1_FPEN);
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}
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static hyp_alternate_select(__fpsimd_is_enabled,
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__fpsimd_enabled_nvhe, __fpsimd_enabled_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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bool __hyp_text __fpsimd_enabled(void)
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{
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return __fpsimd_is_enabled()();
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}
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static void __hyp_text __activate_traps_vhe(void)
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{
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u64 val;
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val = read_sysreg(cpacr_el1);
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val |= CPACR_EL1_TTA;
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val &= ~CPACR_EL1_FPEN;
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write_sysreg(val, cpacr_el1);
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write_sysreg(__kvm_hyp_vector, vbar_el1);
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}
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static void __hyp_text __activate_traps_nvhe(void)
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{
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u64 val;
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val = CPTR_EL2_DEFAULT;
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val |= CPTR_EL2_TTA | CPTR_EL2_TFP;
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write_sysreg(val, cptr_el2);
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}
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static hyp_alternate_select(__activate_traps_arch,
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__activate_traps_nvhe, __activate_traps_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
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{
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u64 val;
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/*
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* We are about to set CPTR_EL2.TFP to trap all floating point
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* register accesses to EL2, however, the ARM ARM clearly states that
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* traps are only taken to EL2 if the operation would not otherwise
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* trap to EL1. Therefore, always make sure that for 32-bit guests,
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* we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
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* If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
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* it will cause an exception.
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*/
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val = vcpu->arch.hcr_el2;
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if (!(val & HCR_RW) && system_supports_fpsimd()) {
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write_sysreg(1 << 30, fpexc32_el2);
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isb();
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}
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write_sysreg(val, hcr_el2);
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/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
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write_sysreg(1 << 15, hstr_el2);
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/*
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* Make sure we trap PMU access from EL0 to EL2. Also sanitize
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* PMSELR_EL0 to make sure it never contains the cycle
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* counter, which could make a PMXEVCNTR_EL0 access UNDEF at
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* EL1 instead of being trapped to EL2.
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*/
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write_sysreg(0, pmselr_el0);
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write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
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write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
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__activate_traps_arch()();
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}
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static void __hyp_text __deactivate_traps_vhe(void)
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{
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extern char vectors[]; /* kernel exception vectors */
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u64 mdcr_el2 = read_sysreg(mdcr_el2);
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mdcr_el2 &= MDCR_EL2_HPMN_MASK |
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MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
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MDCR_EL2_TPMS;
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write_sysreg(mdcr_el2, mdcr_el2);
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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write_sysreg(CPACR_EL1_FPEN, cpacr_el1);
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write_sysreg(vectors, vbar_el1);
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}
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static void __hyp_text __deactivate_traps_nvhe(void)
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{
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u64 mdcr_el2 = read_sysreg(mdcr_el2);
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mdcr_el2 &= MDCR_EL2_HPMN_MASK;
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mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
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write_sysreg(mdcr_el2, mdcr_el2);
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write_sysreg(HCR_RW, hcr_el2);
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write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
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}
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static hyp_alternate_select(__deactivate_traps_arch,
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__deactivate_traps_nvhe, __deactivate_traps_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
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{
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/*
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* If we pended a virtual abort, preserve it until it gets
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* cleared. See D1.14.3 (Virtual Interrupts) for details, but
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* the crucial bit is "On taking a vSError interrupt,
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* HCR_EL2.VSE is cleared to 0."
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*/
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if (vcpu->arch.hcr_el2 & HCR_VSE)
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vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
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__deactivate_traps_arch()();
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write_sysreg(0, hstr_el2);
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write_sysreg(0, pmuserenr_el0);
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}
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static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(vcpu->kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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}
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static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
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{
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write_sysreg(0, vttbr_el2);
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}
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static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
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{
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if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
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__vgic_v3_save_state(vcpu);
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else
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__vgic_v2_save_state(vcpu);
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write_sysreg(read_sysreg(hcr_el2) & ~HCR_INT_OVERRIDE, hcr_el2);
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}
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static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
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{
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u64 val;
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val = read_sysreg(hcr_el2);
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val |= HCR_INT_OVERRIDE;
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val |= vcpu->arch.irq_lines;
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write_sysreg(val, hcr_el2);
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if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
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__vgic_v3_restore_state(vcpu);
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else
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__vgic_v2_restore_state(vcpu);
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}
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static bool __hyp_text __true_value(void)
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{
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return true;
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}
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static bool __hyp_text __false_value(void)
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{
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return false;
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}
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static hyp_alternate_select(__check_arm_834220,
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__false_value, __true_value,
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ARM64_WORKAROUND_834220);
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static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
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{
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u64 par, tmp;
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/*
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* Resolve the IPA the hard way using the guest VA.
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*
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* Stage-1 translation already validated the memory access
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* rights. As such, we can use the EL1 translation regime, and
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* don't have to distinguish between EL0 and EL1 access.
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*
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* We do need to save/restore PAR_EL1 though, as we haven't
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* saved the guest context yet, and we may return early...
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*/
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par = read_sysreg(par_el1);
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asm volatile("at s1e1r, %0" : : "r" (far));
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isb();
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tmp = read_sysreg(par_el1);
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write_sysreg(par, par_el1);
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if (unlikely(tmp & 1))
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return false; /* Translation failed, back to guest */
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/* Convert PAR to HPFAR format */
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*hpfar = ((tmp >> 12) & ((1UL << 36) - 1)) << 4;
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return true;
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}
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static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
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{
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u64 esr = read_sysreg_el2(esr);
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u8 ec = ESR_ELx_EC(esr);
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u64 hpfar, far;
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vcpu->arch.fault.esr_el2 = esr;
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if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
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return true;
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far = read_sysreg_el2(far);
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/*
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* The HPFAR can be invalid if the stage 2 fault did not
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* happen during a stage 1 page table walk (the ESR_EL2.S1PTW
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* bit is clear) and one of the two following cases are true:
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* 1. The fault was due to a permission fault
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* 2. The processor carries errata 834220
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*
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* Therefore, for all non S1PTW faults where we either have a
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* permission fault or the errata workaround is enabled, we
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* resolve the IPA using the AT instruction.
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*/
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if (!(esr & ESR_ELx_S1PTW) &&
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(__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
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if (!__translate_far_to_hpfar(far, &hpfar))
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return false;
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} else {
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hpfar = read_sysreg(hpfar_el2);
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}
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vcpu->arch.fault.far_el2 = far;
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vcpu->arch.fault.hpfar_el2 = hpfar;
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return true;
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}
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static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
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{
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*vcpu_pc(vcpu) = read_sysreg_el2(elr);
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if (vcpu_mode_is_32bit(vcpu)) {
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vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(spsr);
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kvm_skip_instr32(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
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write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, spsr);
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} else {
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*vcpu_pc(vcpu) += 4;
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}
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write_sysreg_el2(*vcpu_pc(vcpu), elr);
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}
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int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *host_ctxt;
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struct kvm_cpu_context *guest_ctxt;
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bool fp_enabled;
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u64 exit_code;
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vcpu = kern_hyp_va(vcpu);
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write_sysreg(vcpu, tpidr_el2);
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host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
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guest_ctxt = &vcpu->arch.ctxt;
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__sysreg_save_host_state(host_ctxt);
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__debug_cond_save_host_state(vcpu);
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__activate_traps(vcpu);
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__activate_vm(vcpu);
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__vgic_restore_state(vcpu);
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__timer_restore_state(vcpu);
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/*
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* We must restore the 32-bit state before the sysregs, thanks
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* to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
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*/
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__sysreg32_restore_state(vcpu);
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__sysreg_restore_guest_state(guest_ctxt);
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__debug_restore_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
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/* Jump in the fire! */
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again:
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exit_code = __guest_enter(vcpu, host_ctxt);
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/* And we're baaack! */
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/*
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* We're using the raw exception code in order to only process
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* the trap if no SError is pending. We will come back to the
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* same PC once the SError has been injected, and replay the
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* trapping instruction.
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*/
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if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu))
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goto again;
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if (static_branch_unlikely(&vgic_v2_cpuif_trap) &&
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exit_code == ARM_EXCEPTION_TRAP) {
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bool valid;
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valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
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kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
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kvm_vcpu_dabt_isvalid(vcpu) &&
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!kvm_vcpu_dabt_isextabt(vcpu) &&
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!kvm_vcpu_dabt_iss1tw(vcpu);
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if (valid) {
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int ret = __vgic_v2_perform_cpuif_access(vcpu);
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if (ret == 1) {
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__skip_instr(vcpu);
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goto again;
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}
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if (ret == -1) {
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/* Promote an illegal access to an SError */
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__skip_instr(vcpu);
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exit_code = ARM_EXCEPTION_EL1_SERROR;
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}
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/* 0 falls through to be handler out of EL2 */
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}
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}
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if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
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exit_code == ARM_EXCEPTION_TRAP &&
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(kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
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kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
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int ret = __vgic_v3_perform_cpuif_access(vcpu);
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if (ret == 1) {
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__skip_instr(vcpu);
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goto again;
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}
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/* 0 falls through to be handled out of EL2 */
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}
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fp_enabled = __fpsimd_enabled();
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__sysreg_save_guest_state(guest_ctxt);
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__sysreg32_save_state(vcpu);
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__timer_save_state(vcpu);
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__vgic_save_state(vcpu);
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__deactivate_traps(vcpu);
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__deactivate_vm(vcpu);
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__sysreg_restore_host_state(host_ctxt);
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if (fp_enabled) {
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__fpsimd_save_state(&guest_ctxt->gp_regs.fp_regs);
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__fpsimd_restore_state(&host_ctxt->gp_regs.fp_regs);
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}
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__debug_save_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
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/*
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* This must come after restoring the host sysregs, since a non-VHE
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* system may enable SPE here and make use of the TTBRs.
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*/
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__debug_cond_restore_host_state(vcpu);
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return exit_code;
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}
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static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
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static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par)
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{
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unsigned long str_va;
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/*
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* Force the panic string to be loaded from the literal pool,
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* making sure it is a kernel address and not a PC-relative
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* reference.
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*/
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asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
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__hyp_do_panic(str_va,
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spsr, elr,
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read_sysreg(esr_el2), read_sysreg_el2(far),
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read_sysreg(hpfar_el2), par,
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(void *)read_sysreg(tpidr_el2));
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}
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static void __hyp_text __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par)
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{
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panic(__hyp_panic_string,
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spsr, elr,
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read_sysreg_el2(esr), read_sysreg_el2(far),
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read_sysreg(hpfar_el2), par,
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(void *)read_sysreg(tpidr_el2));
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}
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static hyp_alternate_select(__hyp_call_panic,
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__hyp_call_panic_nvhe, __hyp_call_panic_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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void __hyp_text __noreturn __hyp_panic(void)
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{
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u64 spsr = read_sysreg_el2(spsr);
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u64 elr = read_sysreg_el2(elr);
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u64 par = read_sysreg(par_el1);
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if (read_sysreg(vttbr_el2)) {
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struct kvm_vcpu *vcpu;
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struct kvm_cpu_context *host_ctxt;
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vcpu = (struct kvm_vcpu *)read_sysreg(tpidr_el2);
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host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
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__timer_save_state(vcpu);
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__deactivate_traps(vcpu);
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__deactivate_vm(vcpu);
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__sysreg_restore_host_state(host_ctxt);
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}
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/* Call panic for real */
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__hyp_call_panic()(spsr, elr, par);
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unreachable();
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}
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