396 lines
10 KiB
C
396 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Cadence Sierra PHY Driver
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*
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* Copyright (c) 2018 Cadence Design Systems
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* Author: Alan Douglas <adouglas@cadence.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <dt-bindings/phy/phy.h>
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/* PHY register offsets */
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#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
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#define SIERRA_DET_STANDEC_A (0x4000 << 2)
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#define SIERRA_DET_STANDEC_B (0x4001 << 2)
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#define SIERRA_DET_STANDEC_C (0x4002 << 2)
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#define SIERRA_DET_STANDEC_D (0x4003 << 2)
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#define SIERRA_DET_STANDEC_E (0x4004 << 2)
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#define SIERRA_PSM_LANECAL (0x4008 << 2)
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#define SIERRA_PSM_DIAG (0x4015 << 2)
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#define SIERRA_PSC_TX_A0 (0x4028 << 2)
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#define SIERRA_PSC_TX_A1 (0x4029 << 2)
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#define SIERRA_PSC_TX_A2 (0x402A << 2)
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#define SIERRA_PSC_TX_A3 (0x402B << 2)
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#define SIERRA_PSC_RX_A0 (0x4030 << 2)
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#define SIERRA_PSC_RX_A1 (0x4031 << 2)
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#define SIERRA_PSC_RX_A2 (0x4032 << 2)
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#define SIERRA_PSC_RX_A3 (0x4033 << 2)
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#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
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#define SIERRA_PLLCTRL_GEN_D (0x403E << 2)
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#define SIERRA_DRVCTRL_ATTEN (0x406A << 2)
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#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
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#define SIERRA_RX_CREQ_FLTR_A_MODE1 (0x4087 << 2)
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#define SIERRA_RX_CREQ_FLTR_A_MODE0 (0x4088 << 2)
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#define SIERRA_CREQ_CCLKDET_MODE01 (0x408E << 2)
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#define SIERRA_RX_CTLE_MAINTENANCE (0x4091 << 2)
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#define SIERRA_CREQ_FSMCLK_SEL (0x4092 << 2)
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#define SIERRA_CTLELUT_CTRL (0x4098 << 2)
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#define SIERRA_DFE_ECMP_RATESEL (0x40C0 << 2)
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#define SIERRA_DFE_SMP_RATESEL (0x40C1 << 2)
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#define SIERRA_DEQ_VGATUNE_CTRL (0x40E1 << 2)
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#define SIERRA_TMRVAL_MODE3 (0x416E << 2)
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#define SIERRA_TMRVAL_MODE2 (0x416F << 2)
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#define SIERRA_TMRVAL_MODE1 (0x4170 << 2)
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#define SIERRA_TMRVAL_MODE0 (0x4171 << 2)
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#define SIERRA_PICNT_MODE1 (0x4174 << 2)
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#define SIERRA_CPI_OUTBUF_RATESEL (0x417C << 2)
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#define SIERRA_LFPSFILT_NS (0x418A << 2)
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#define SIERRA_LFPSFILT_RD (0x418B << 2)
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#define SIERRA_LFPSFILT_MP (0x418C << 2)
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#define SIERRA_SDFILT_H2L_A (0x4191 << 2)
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#define SIERRA_MACRO_ID 0x00007364
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#define SIERRA_MAX_LANES 4
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struct cdns_sierra_inst {
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struct phy *phy;
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u32 phy_type;
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u32 num_lanes;
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u32 mlane;
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struct reset_control *lnk_rst;
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};
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struct cdns_reg_pairs {
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u16 val;
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u32 off;
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};
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struct cdns_sierra_data {
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u32 id_value;
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u32 pcie_regs;
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u32 usb_regs;
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struct cdns_reg_pairs *pcie_vals;
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struct cdns_reg_pairs *usb_vals;
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};
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struct cdns_sierra_phy {
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struct device *dev;
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void __iomem *base;
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struct cdns_sierra_data *init_data;
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struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
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struct reset_control *phy_rst;
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struct reset_control *apb_rst;
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struct clk *clk;
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int nsubnodes;
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bool autoconf;
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};
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static void cdns_sierra_phy_init(struct phy *gphy)
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{
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struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
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struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
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int i, j;
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struct cdns_reg_pairs *vals;
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u32 num_regs;
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if (ins->phy_type == PHY_TYPE_PCIE) {
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num_regs = phy->init_data->pcie_regs;
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vals = phy->init_data->pcie_vals;
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} else if (ins->phy_type == PHY_TYPE_USB3) {
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num_regs = phy->init_data->usb_regs;
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vals = phy->init_data->usb_vals;
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} else {
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return;
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}
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for (i = 0; i < ins->num_lanes; i++)
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for (j = 0; j < num_regs ; j++)
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writel(vals[j].val, phy->base +
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vals[j].off + (i + ins->mlane) * 0x800);
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}
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static int cdns_sierra_phy_on(struct phy *gphy)
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{
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struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
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/* Take the PHY lane group out of reset */
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return reset_control_deassert(ins->lnk_rst);
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}
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static int cdns_sierra_phy_off(struct phy *gphy)
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{
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struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
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return reset_control_assert(ins->lnk_rst);
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}
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static const struct phy_ops ops = {
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.power_on = cdns_sierra_phy_on,
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.power_off = cdns_sierra_phy_off,
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.owner = THIS_MODULE,
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};
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static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
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struct device_node *child)
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{
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if (of_property_read_u32(child, "reg", &inst->mlane))
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return -EINVAL;
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if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
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return -EINVAL;
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if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type))
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return -EINVAL;
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return 0;
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}
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static const struct of_device_id cdns_sierra_id_table[];
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static int cdns_sierra_phy_probe(struct platform_device *pdev)
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{
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struct cdns_sierra_phy *sp;
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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struct resource *res;
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int i, ret, node = 0;
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struct device_node *dn = dev->of_node, *child;
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if (of_get_child_count(dn) == 0)
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return -ENODEV;
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sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
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if (!sp)
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return -ENOMEM;
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dev_set_drvdata(dev, sp);
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sp->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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sp->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(sp->base)) {
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dev_err(dev, "missing \"reg\"\n");
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return PTR_ERR(sp->base);
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}
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/* Get init data for this PHY */
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match = of_match_device(cdns_sierra_id_table, dev);
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if (!match)
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return -EINVAL;
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sp->init_data = (struct cdns_sierra_data *)match->data;
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platform_set_drvdata(pdev, sp);
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sp->clk = devm_clk_get(dev, "phy_clk");
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if (IS_ERR(sp->clk)) {
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dev_err(dev, "failed to get clock phy_clk\n");
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return PTR_ERR(sp->clk);
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}
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sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
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if (IS_ERR(sp->phy_rst)) {
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dev_err(dev, "failed to get reset\n");
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return PTR_ERR(sp->phy_rst);
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}
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sp->apb_rst = devm_reset_control_get(dev, "sierra_apb");
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if (IS_ERR(sp->apb_rst)) {
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dev_err(dev, "failed to get apb reset\n");
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return PTR_ERR(sp->apb_rst);
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}
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ret = clk_prepare_enable(sp->clk);
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if (ret)
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return ret;
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/* Enable APB */
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reset_control_deassert(sp->apb_rst);
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/* Check that PHY is present */
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if (sp->init_data->id_value != readl(sp->base)) {
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ret = -EINVAL;
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goto clk_disable;
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}
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sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");
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for_each_available_child_of_node(dn, child) {
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struct phy *gphy;
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sp->phys[node].lnk_rst =
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of_reset_control_get_exclusive_by_index(child, 0);
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if (IS_ERR(sp->phys[node].lnk_rst)) {
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dev_err(dev, "failed to get reset %s\n",
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child->full_name);
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ret = PTR_ERR(sp->phys[node].lnk_rst);
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goto put_child2;
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}
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if (!sp->autoconf) {
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ret = cdns_sierra_get_optional(&sp->phys[node], child);
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if (ret) {
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dev_err(dev, "missing property in node %s\n",
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child->name);
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goto put_child;
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}
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}
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gphy = devm_phy_create(dev, child, &ops);
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if (IS_ERR(gphy)) {
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ret = PTR_ERR(gphy);
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goto put_child;
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}
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sp->phys[node].phy = gphy;
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phy_set_drvdata(gphy, &sp->phys[node]);
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/* Initialise the PHY registers, unless auto configured */
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if (!sp->autoconf)
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cdns_sierra_phy_init(gphy);
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node++;
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}
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sp->nsubnodes = node;
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/* If more than one subnode, configure the PHY as multilink */
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if (!sp->autoconf && sp->nsubnodes > 1)
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writel(2, sp->base + SIERRA_PHY_PLL_CFG);
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pm_runtime_enable(dev);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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reset_control_deassert(sp->phy_rst);
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return PTR_ERR_OR_ZERO(phy_provider);
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put_child:
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node++;
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put_child2:
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for (i = 0; i < node; i++)
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reset_control_put(sp->phys[i].lnk_rst);
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of_node_put(child);
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clk_disable:
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clk_disable_unprepare(sp->clk);
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reset_control_assert(sp->apb_rst);
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return ret;
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}
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static int cdns_sierra_phy_remove(struct platform_device *pdev)
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{
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struct cdns_sierra_phy *phy = dev_get_drvdata(pdev->dev.parent);
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int i;
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reset_control_assert(phy->phy_rst);
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reset_control_assert(phy->apb_rst);
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pm_runtime_disable(&pdev->dev);
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/*
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* The device level resets will be put automatically.
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* Need to put the subnode resets here though.
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*/
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for (i = 0; i < phy->nsubnodes; i++) {
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reset_control_assert(phy->phys[i].lnk_rst);
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reset_control_put(phy->phys[i].lnk_rst);
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}
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return 0;
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}
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static struct cdns_reg_pairs cdns_usb_regs[] = {
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/*
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* Write USB configuration parameters to the PHY.
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* These values are specific to this specific hardware
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* configuration.
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*/
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{0xFE0A, SIERRA_DET_STANDEC_A},
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{0x000F, SIERRA_DET_STANDEC_B},
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{0x55A5, SIERRA_DET_STANDEC_C},
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{0x69AD, SIERRA_DET_STANDEC_D},
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{0x0241, SIERRA_DET_STANDEC_E},
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{0x0110, SIERRA_PSM_LANECAL},
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{0xCF00, SIERRA_PSM_DIAG},
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{0x001F, SIERRA_PSC_TX_A0},
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{0x0007, SIERRA_PSC_TX_A1},
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{0x0003, SIERRA_PSC_TX_A2},
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{0x0003, SIERRA_PSC_TX_A3},
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{0x0FFF, SIERRA_PSC_RX_A0},
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{0x0003, SIERRA_PSC_RX_A1},
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{0x0003, SIERRA_PSC_RX_A2},
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{0x0001, SIERRA_PSC_RX_A3},
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{0x0001, SIERRA_PLLCTRL_SUBRATE},
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{0x0406, SIERRA_PLLCTRL_GEN_D},
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{0x0000, SIERRA_DRVCTRL_ATTEN},
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{0x823E, SIERRA_CLKPATHCTRL_TMR},
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{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1},
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{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0},
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{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01},
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{0x023C, SIERRA_RX_CTLE_MAINTENANCE},
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{0x3232, SIERRA_CREQ_FSMCLK_SEL},
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{0x8452, SIERRA_CTLELUT_CTRL},
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{0x4121, SIERRA_DFE_ECMP_RATESEL},
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{0x4121, SIERRA_DFE_SMP_RATESEL},
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{0x9999, SIERRA_DEQ_VGATUNE_CTRL},
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{0x0330, SIERRA_TMRVAL_MODE0},
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{0x01FF, SIERRA_PICNT_MODE1},
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{0x0009, SIERRA_CPI_OUTBUF_RATESEL},
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{0x000F, SIERRA_LFPSFILT_NS},
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{0x0009, SIERRA_LFPSFILT_RD},
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{0x0001, SIERRA_LFPSFILT_MP},
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{0x8013, SIERRA_SDFILT_H2L_A},
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{0x0400, SIERRA_TMRVAL_MODE1},
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};
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static struct cdns_reg_pairs cdns_pcie_regs[] = {
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/*
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* Write PCIe configuration parameters to the PHY.
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* These values are specific to this specific hardware
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* configuration.
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*/
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{0x891f, SIERRA_DET_STANDEC_D},
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{0x0053, SIERRA_DET_STANDEC_E},
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{0x0400, SIERRA_TMRVAL_MODE2},
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{0x0200, SIERRA_TMRVAL_MODE3},
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};
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static const struct cdns_sierra_data cdns_map_sierra = {
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SIERRA_MACRO_ID,
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ARRAY_SIZE(cdns_pcie_regs),
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ARRAY_SIZE(cdns_usb_regs),
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cdns_pcie_regs,
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cdns_usb_regs
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};
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static const struct of_device_id cdns_sierra_id_table[] = {
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{
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.compatible = "cdns,sierra-phy-t0",
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.data = &cdns_map_sierra,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);
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static struct platform_driver cdns_sierra_driver = {
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.probe = cdns_sierra_phy_probe,
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.remove = cdns_sierra_phy_remove,
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.driver = {
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.name = "cdns-sierra-phy",
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.of_match_table = cdns_sierra_id_table,
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},
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};
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module_platform_driver(cdns_sierra_driver);
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MODULE_ALIAS("platform:cdns_sierra");
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MODULE_AUTHOR("Cadence Design Systems");
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MODULE_DESCRIPTION("CDNS sierra phy driver");
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MODULE_LICENSE("GPL v2");
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