493 lines
12 KiB
C
493 lines
12 KiB
C
/*
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* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/io.h>
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#include <linux/rtc.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <mach/hardware.h>
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#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
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#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
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#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
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#define RTC_SW_BIT (1 << 0)
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#define RTC_ALM_BIT (1 << 2)
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#define RTC_1HZ_BIT (1 << 4)
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#define RTC_2HZ_BIT (1 << 7)
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#define RTC_SAM0_BIT (1 << 8)
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#define RTC_SAM1_BIT (1 << 9)
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#define RTC_SAM2_BIT (1 << 10)
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#define RTC_SAM3_BIT (1 << 11)
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#define RTC_SAM4_BIT (1 << 12)
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#define RTC_SAM5_BIT (1 << 13)
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#define RTC_SAM6_BIT (1 << 14)
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#define RTC_SAM7_BIT (1 << 15)
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#define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
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RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
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RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
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#define RTC_ENABLE_BIT (1 << 7)
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#define MAX_PIE_NUM 9
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#define MAX_PIE_FREQ 512
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static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
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{ 2, RTC_2HZ_BIT },
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{ 4, RTC_SAM0_BIT },
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{ 8, RTC_SAM1_BIT },
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{ 16, RTC_SAM2_BIT },
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{ 32, RTC_SAM3_BIT },
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{ 64, RTC_SAM4_BIT },
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{ 128, RTC_SAM5_BIT },
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{ 256, RTC_SAM6_BIT },
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{ MAX_PIE_FREQ, RTC_SAM7_BIT },
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};
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#define MXC_RTC_TIME 0
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#define MXC_RTC_ALARM 1
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#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
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#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
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#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
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#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
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#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
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#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
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#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
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#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
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#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
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#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
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#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
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#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
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#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
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struct rtc_plat_data {
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struct rtc_device *rtc;
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void __iomem *ioaddr;
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int irq;
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struct clk *clk;
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struct rtc_time g_rtc_alarm;
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};
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/*
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* This function is used to obtain the RTC time or the alarm value in
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* second.
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*/
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static u32 get_alarm_or_time(struct device *dev, int time_alarm)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
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switch (time_alarm) {
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case MXC_RTC_TIME:
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day = readw(ioaddr + RTC_DAYR);
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hr_min = readw(ioaddr + RTC_HOURMIN);
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sec = readw(ioaddr + RTC_SECOND);
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break;
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case MXC_RTC_ALARM:
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day = readw(ioaddr + RTC_DAYALARM);
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hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
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sec = readw(ioaddr + RTC_ALRM_SEC);
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break;
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}
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hr = hr_min >> 8;
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min = hr_min & 0xff;
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return (((day * 24 + hr) * 60) + min) * 60 + sec;
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}
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/*
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* This function sets the RTC alarm value or the time value.
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*/
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static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time)
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{
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u32 day, hr, min, sec, temp;
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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day = time / 86400;
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time -= day * 86400;
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/* time is within a day now */
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hr = time / 3600;
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time -= hr * 3600;
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/* time is within an hour now */
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min = time / 60;
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sec = time - min * 60;
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temp = (hr << 8) + min;
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switch (time_alarm) {
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case MXC_RTC_TIME:
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writew(day, ioaddr + RTC_DAYR);
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writew(sec, ioaddr + RTC_SECOND);
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writew(temp, ioaddr + RTC_HOURMIN);
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break;
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case MXC_RTC_ALARM:
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writew(day, ioaddr + RTC_DAYALARM);
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writew(sec, ioaddr + RTC_ALRM_SEC);
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writew(temp, ioaddr + RTC_ALRM_HM);
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break;
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}
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}
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/*
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* This function updates the RTC alarm registers and then clears all the
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* interrupt status bits.
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*/
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static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
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{
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struct rtc_time alarm_tm, now_tm;
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unsigned long now, time;
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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now = get_alarm_or_time(dev, MXC_RTC_TIME);
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rtc_time_to_tm(now, &now_tm);
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alarm_tm.tm_year = now_tm.tm_year;
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alarm_tm.tm_mon = now_tm.tm_mon;
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alarm_tm.tm_mday = now_tm.tm_mday;
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alarm_tm.tm_hour = alrm->tm_hour;
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alarm_tm.tm_min = alrm->tm_min;
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alarm_tm.tm_sec = alrm->tm_sec;
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rtc_tm_to_time(&alarm_tm, &time);
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/* clear all the interrupt status bits */
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writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
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set_alarm_or_time(dev, MXC_RTC_ALARM, time);
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return 0;
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}
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static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
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unsigned int enabled)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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u32 reg;
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spin_lock_irq(&pdata->rtc->irq_lock);
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reg = readw(ioaddr + RTC_RTCIENR);
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if (enabled)
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reg |= bit;
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else
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reg &= ~bit;
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writew(reg, ioaddr + RTC_RTCIENR);
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spin_unlock_irq(&pdata->rtc->irq_lock);
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}
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/* This function is the RTC interrupt service routine. */
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static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
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{
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struct platform_device *pdev = dev_id;
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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unsigned long flags;
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u32 status;
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u32 events = 0;
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spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
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status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
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/* clear interrupt sources */
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writew(status, ioaddr + RTC_RTCISR);
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/* update irq data & counter */
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if (status & RTC_ALM_BIT) {
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events |= (RTC_AF | RTC_IRQF);
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/* RTC alarm should be one-shot */
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mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
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}
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if (status & RTC_1HZ_BIT)
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events |= (RTC_UF | RTC_IRQF);
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if (status & PIT_ALL_ON)
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events |= (RTC_PF | RTC_IRQF);
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rtc_update_irq(pdata->rtc, 1, events);
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spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
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return IRQ_HANDLED;
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}
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/*
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* Clear all interrupts and release the IRQ
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*/
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static void mxc_rtc_release(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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spin_lock_irq(&pdata->rtc->irq_lock);
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/* Disable all rtc interrupts */
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writew(0, ioaddr + RTC_RTCIENR);
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/* Clear all interrupt status */
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writew(0xffffffff, ioaddr + RTC_RTCISR);
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spin_unlock_irq(&pdata->rtc->irq_lock);
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}
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static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
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return 0;
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}
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/*
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* This function reads the current RTC time into tm in Gregorian date.
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*/
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static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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u32 val;
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/* Avoid roll-over from reading the different registers */
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do {
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val = get_alarm_or_time(dev, MXC_RTC_TIME);
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} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
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rtc_time_to_tm(val, tm);
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return 0;
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}
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/*
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* This function sets the internal RTC time based on tm in Gregorian date.
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*/
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static int mxc_rtc_set_mmss(struct device *dev, unsigned long time)
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{
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/*
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* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
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*/
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if (cpu_is_mx1()) {
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struct rtc_time tm;
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rtc_time_to_tm(time, &tm);
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tm.tm_year = 70;
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rtc_tm_to_time(&tm, &time);
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}
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/* Avoid roll-over from reading the different registers */
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do {
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set_alarm_or_time(dev, MXC_RTC_TIME, time);
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} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
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return 0;
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}
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/*
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* This function reads the current alarm value into the passed in 'alrm'
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* argument. It updates the alrm's pending field value based on the whether
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* an alarm interrupt occurs or not.
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*/
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static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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void __iomem *ioaddr = pdata->ioaddr;
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rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
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alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
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return 0;
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}
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/*
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* This function sets the RTC alarm based on passed in alrm.
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*/
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static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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int ret;
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ret = rtc_update_alarm(dev, &alrm->time);
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if (ret)
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return ret;
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memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
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mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
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return 0;
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}
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/* RTC layer */
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static struct rtc_class_ops mxc_rtc_ops = {
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.release = mxc_rtc_release,
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.read_time = mxc_rtc_read_time,
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.set_mmss = mxc_rtc_set_mmss,
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.read_alarm = mxc_rtc_read_alarm,
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.set_alarm = mxc_rtc_set_alarm,
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.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
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};
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static int __devinit mxc_rtc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct rtc_device *rtc;
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struct rtc_plat_data *pdata = NULL;
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u32 reg;
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unsigned long rate;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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if (!devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), pdev->name))
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return -EBUSY;
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pdata->ioaddr = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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pdata->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pdata->clk)) {
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dev_err(&pdev->dev, "unable to get clock!\n");
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ret = PTR_ERR(pdata->clk);
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goto exit_free_pdata;
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}
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clk_prepare_enable(pdata->clk);
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rate = clk_get_rate(pdata->clk);
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if (rate == 32768)
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reg = RTC_INPUT_CLK_32768HZ;
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else if (rate == 32000)
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reg = RTC_INPUT_CLK_32000HZ;
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else if (rate == 38400)
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reg = RTC_INPUT_CLK_38400HZ;
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else {
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dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
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ret = -EINVAL;
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goto exit_put_clk;
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}
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reg |= RTC_ENABLE_BIT;
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writew(reg, (pdata->ioaddr + RTC_RTCCTL));
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if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
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dev_err(&pdev->dev, "hardware module can't be enabled!\n");
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ret = -EIO;
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goto exit_put_clk;
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}
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platform_set_drvdata(pdev, pdata);
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/* Configure and enable the RTC */
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pdata->irq = platform_get_irq(pdev, 0);
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if (pdata->irq >= 0 &&
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devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
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IRQF_SHARED, pdev->name, pdev) < 0) {
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dev_warn(&pdev->dev, "interrupt not available.\n");
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pdata->irq = -1;
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}
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if (pdata->irq >=0)
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device_init_wakeup(&pdev->dev, 1);
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rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops,
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THIS_MODULE);
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if (IS_ERR(rtc)) {
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ret = PTR_ERR(rtc);
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goto exit_clr_drvdata;
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}
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pdata->rtc = rtc;
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return 0;
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exit_clr_drvdata:
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platform_set_drvdata(pdev, NULL);
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exit_put_clk:
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clk_disable_unprepare(pdata->clk);
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exit_free_pdata:
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return ret;
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}
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static int __devexit mxc_rtc_remove(struct platform_device *pdev)
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{
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struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
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rtc_device_unregister(pdata->rtc);
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clk_disable_unprepare(pdata->clk);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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#ifdef CONFIG_PM
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static int mxc_rtc_suspend(struct device *dev)
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{
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struct rtc_plat_data *pdata = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(pdata->irq);
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return 0;
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}
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static int mxc_rtc_resume(struct device *dev)
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{
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struct rtc_plat_data *pdata = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(pdata->irq);
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return 0;
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}
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static struct dev_pm_ops mxc_rtc_pm_ops = {
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.suspend = mxc_rtc_suspend,
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.resume = mxc_rtc_resume,
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};
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#endif
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static struct platform_driver mxc_rtc_driver = {
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.driver = {
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.name = "mxc_rtc",
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#ifdef CONFIG_PM
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.pm = &mxc_rtc_pm_ops,
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#endif
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.owner = THIS_MODULE,
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},
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.probe = mxc_rtc_probe,
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.remove = __devexit_p(mxc_rtc_remove),
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};
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module_platform_driver(mxc_rtc_driver)
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MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
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MODULE_DESCRIPTION("RTC driver for Freescale MXC");
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MODULE_LICENSE("GPL");
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