220 lines
5.2 KiB
C
220 lines
5.2 KiB
C
/*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CLK_IPROC_H
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#define _CLK_IPROC_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/clk-provider.h>
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#define IPROC_CLK_NAME_LEN 25
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#define IPROC_CLK_INVALID_OFFSET 0xffffffff
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#define bit_mask(width) ((1 << (width)) - 1)
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/* clocks that should not be disabled at runtime */
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#define IPROC_CLK_AON BIT(0)
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/* PLL that requires gating through ASIU */
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#define IPROC_CLK_PLL_ASIU BIT(1)
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/* PLL that has fractional part of the NDIV */
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#define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
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/*
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* Some of the iProc PLL/clocks may have an ASIC bug that requires read back
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* of the same register following the write to flush the write transaction into
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* the intended register
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*/
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#define IPROC_CLK_NEEDS_READ_BACK BIT(3)
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/*
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* Some PLLs require the PLL SW override bit to be set before changes can be
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* applied to the PLL
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*/
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#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
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/*
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* Some PLLs use a different way to control clock power, via the PWRDWN bit in
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* the PLL control register
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*/
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#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
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/*
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* Some PLLs have separate registers for Status and Control. Identify this to
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* let the driver know if additional registers need to be used
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*/
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#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)
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/*
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* Some PLLs have an additional divide by 2 in master clock calculation;
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* MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know
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* of modified calculations
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*/
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#define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)
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/*
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* Some PLLs provide a look up table for the leaf clock frequencies and
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* auto calculates VCO frequency parameters based on the provided leaf
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* clock frequencies. They have a user mode that allows the divider
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* controls to be determined by the user
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*/
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#define IPROC_CLK_PLL_USER_MODE_ON BIT(8)
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/*
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* Some PLLs have an active low reset
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*/
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#define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
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/*
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* Parameters for VCO frequency configuration
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*
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* VCO frequency =
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* ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
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*/
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struct iproc_pll_vco_param {
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unsigned long rate;
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unsigned int ndiv_int;
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unsigned int ndiv_frac;
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unsigned int pdiv;
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};
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struct iproc_clk_reg_op {
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unsigned int offset;
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unsigned int shift;
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unsigned int width;
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};
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/*
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* Clock gating control at the top ASIU level
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*/
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struct iproc_asiu_gate {
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unsigned int offset;
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unsigned int en_shift;
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};
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/*
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* Control of powering on/off of a PLL
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*
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* Before powering off a PLL, input isolation (ISO) needs to be enabled
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*/
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struct iproc_pll_aon_pwr_ctrl {
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unsigned int offset;
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unsigned int pwr_width;
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unsigned int pwr_shift;
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unsigned int iso_shift;
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};
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/*
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* Control of the PLL reset
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*/
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struct iproc_pll_reset_ctrl {
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unsigned int offset;
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unsigned int reset_shift;
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unsigned int p_reset_shift;
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};
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/*
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* Control of the Ki, Kp, and Ka parameters
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*/
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struct iproc_pll_dig_filter_ctrl {
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unsigned int offset;
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unsigned int ki_shift;
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unsigned int ki_width;
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unsigned int kp_shift;
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unsigned int kp_width;
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unsigned int ka_shift;
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unsigned int ka_width;
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};
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/*
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* To enable SW control of the PLL
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*/
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struct iproc_pll_sw_ctrl {
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unsigned int offset;
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unsigned int shift;
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};
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struct iproc_pll_vco_ctrl {
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unsigned int u_offset;
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unsigned int l_offset;
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};
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/*
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* Main PLL control parameters
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*/
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struct iproc_pll_ctrl {
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unsigned long flags;
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struct iproc_pll_aon_pwr_ctrl aon;
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struct iproc_asiu_gate asiu;
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struct iproc_pll_reset_ctrl reset;
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struct iproc_pll_dig_filter_ctrl dig_filter;
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struct iproc_pll_sw_ctrl sw_ctrl;
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struct iproc_clk_reg_op ndiv_int;
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struct iproc_clk_reg_op ndiv_frac;
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struct iproc_clk_reg_op pdiv;
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struct iproc_pll_vco_ctrl vco_ctrl;
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struct iproc_clk_reg_op status;
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struct iproc_clk_reg_op macro_mode;
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};
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/*
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* Controls enabling/disabling a PLL derived clock
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*/
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struct iproc_clk_enable_ctrl {
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unsigned int offset;
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unsigned int enable_shift;
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unsigned int hold_shift;
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unsigned int bypass_shift;
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};
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/*
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* Main clock control parameters for clocks derived from the PLLs
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*/
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struct iproc_clk_ctrl {
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unsigned int channel;
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unsigned long flags;
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struct iproc_clk_enable_ctrl enable;
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struct iproc_clk_reg_op mdiv;
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};
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/*
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* Divisor of the ASIU clocks
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*/
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struct iproc_asiu_div {
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unsigned int offset;
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unsigned int en_shift;
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unsigned int high_shift;
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unsigned int high_width;
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unsigned int low_shift;
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unsigned int low_width;
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};
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void iproc_armpll_setup(struct device_node *node);
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void iproc_pll_clk_setup(struct device_node *node,
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const struct iproc_pll_ctrl *pll_ctrl,
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const struct iproc_pll_vco_param *vco,
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unsigned int num_vco_entries,
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const struct iproc_clk_ctrl *clk_ctrl,
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unsigned int num_clks);
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void iproc_asiu_setup(struct device_node *node,
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const struct iproc_asiu_div *div,
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const struct iproc_asiu_gate *gate,
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unsigned int num_clks);
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#endif /* _CLK_IPROC_H */
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