285 lines
7.7 KiB
C
285 lines
7.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV architectural definitions
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*
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* Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef __ASM_X86_UV_HUB_H__
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#define __ASM_X86_UV_HUB_H__
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#include <linux/numa.h>
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#include <linux/percpu.h>
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#include <asm/types.h>
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#include <asm/percpu.h>
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/*
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* Addressing Terminology
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*
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* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
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* routers always have low bit of 1, C/MBricks have low bit
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* equal to 0. Most addressing macros that target UV hub chips
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* right shift the NASID by 1 to exclude the always-zero bit.
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*
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* SNASID - NASID right shifted by 1 bit.
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*
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*
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* Memory/UV-HUB Processor Socket Address Format:
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* +--------+---------------+---------------------+
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* |00..0000| SNASID | NodeOffset |
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* +--------+---------------+---------------------+
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* <--- N bits --->|<--------M bits ----->
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*
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* M number of node offset bits (35 .. 40)
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* N number of SNASID bits (0 .. 10)
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*
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* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
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* The actual values are configuration dependent and are set at
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* boot time
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*
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* APICID format
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* NOTE!!!!!! This is the current format of the APICID. However, code
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* should assume that this will change in the future. Use functions
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* in this file for all APICID bit manipulations and conversion.
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*
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* 1111110000000000
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* 5432109876543210
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* nnnnnnnnnnlc0cch
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* sssssssssss
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*
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* n = snasid bits
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* l = socket number on board
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* c = core
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* h = hyperthread
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* s = bits that are in the socket CSR
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*
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* Note: Processor only supports 12 bits in the APICID register. The ACPI
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* tables hold all 16 bits. Software needs to be aware of this.
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*
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* Unless otherwise specified, all references to APICID refer to
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* the FULL value contained in ACPI tables, not the subset in the
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* processor APICID register.
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*/
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/*
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* Maximum number of bricks in all partitions and in all coherency domains.
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* This is the total number of bricks accessible in the numalink fabric. It
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* includes all C & M bricks. Routers are NOT included.
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*
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* This value is also the value of the maximum number of non-router NASIDs
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* in the numalink fabric.
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*
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* NOTE: a brick may be 1 or 2 OS nodes. Don't get these confused.
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*/
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#define UV_MAX_NUMALINK_BLADES 16384
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/*
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* Maximum number of C/Mbricks within a software SSI (hardware may support
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* more).
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*/
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#define UV_MAX_SSI_BLADES 256
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/*
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* The largest possible NASID of a C or M brick (+ 2)
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*/
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#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
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/*
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* The following defines attributes of the HUB chip. These attributes are
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* frequently referenced and are kept in the per-cpu data areas of each cpu.
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* They are kept together in a struct to minimize cache misses.
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*/
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struct uv_hub_info_s {
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unsigned long global_mmr_base;
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unsigned short local_nasid;
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unsigned short gnode_upper;
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unsigned short coherency_domain_number;
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unsigned short numa_blade_id;
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unsigned char blade_processor_id;
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unsigned char m_val;
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unsigned char n_val;
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};
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DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
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#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
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/*
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* Local & Global MMR space macros.
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* Note: macros are intended to be used ONLY by inline functions
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* in this file - not by other kernel code.
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*/
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#define UV_SNASID(n) ((n) >> 1)
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#define UV_NASID(n) ((n) << 1)
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#define UV_LOCAL_MMR_BASE 0xf4000000UL
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#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
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#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
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#define UV_GLOBAL_MMR32_SNASID_MASK 0x3ff
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#define UV_GLOBAL_MMR32_SNASID_SHIFT 15
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#define UV_GLOBAL_MMR64_SNASID_SHIFT 26
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#define UV_GLOBAL_MMR32_NASID_BITS(n) \
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(((UV_SNASID(n) & UV_GLOBAL_MMR32_SNASID_MASK)) << \
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(UV_GLOBAL_MMR32_SNASID_SHIFT))
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#define UV_GLOBAL_MMR64_NASID_BITS(n) \
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((unsigned long)UV_SNASID(n) << UV_GLOBAL_MMR64_SNASID_SHIFT)
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#define UV_APIC_NASID_SHIFT 6
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/*
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* Extract a NASID from an APICID (full apicid, not processor subset)
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*/
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static inline int uv_apicid_to_nasid(int apicid)
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{
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return (UV_NASID(apicid >> UV_APIC_NASID_SHIFT));
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}
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/*
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* Access global MMRs using the low memory MMR32 space. This region supports
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* faster MMR access but not all MMRs are accessible in this space.
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*/
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static inline unsigned long *uv_global_mmr32_address(int nasid,
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unsigned long offset)
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{
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return __va(UV_GLOBAL_MMR32_BASE |
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UV_GLOBAL_MMR32_NASID_BITS(nasid) | offset);
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}
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static inline void uv_write_global_mmr32(int nasid, unsigned long offset,
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unsigned long val)
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{
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*uv_global_mmr32_address(nasid, offset) = val;
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}
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static inline unsigned long uv_read_global_mmr32(int nasid,
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unsigned long offset)
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{
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return *uv_global_mmr32_address(nasid, offset);
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}
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/*
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* Access Global MMR space using the MMR space located at the top of physical
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* memory.
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*/
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static inline unsigned long *uv_global_mmr64_address(int nasid,
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unsigned long offset)
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{
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return __va(UV_GLOBAL_MMR64_BASE |
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UV_GLOBAL_MMR64_NASID_BITS(nasid) | offset);
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}
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static inline void uv_write_global_mmr64(int nasid, unsigned long offset,
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unsigned long val)
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{
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*uv_global_mmr64_address(nasid, offset) = val;
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}
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static inline unsigned long uv_read_global_mmr64(int nasid,
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unsigned long offset)
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{
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return *uv_global_mmr64_address(nasid, offset);
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}
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/*
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* Access node local MMRs. Faster than using global space but only local MMRs
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* are accessible.
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*/
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static inline unsigned long *uv_local_mmr_address(unsigned long offset)
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{
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return __va(UV_LOCAL_MMR_BASE | offset);
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}
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static inline unsigned long uv_read_local_mmr(unsigned long offset)
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{
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return *uv_local_mmr_address(offset);
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}
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static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
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{
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*uv_local_mmr_address(offset) = val;
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}
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/*
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* Structures and definitions for converting between cpu, node, and blade
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* numbers.
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*/
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struct uv_blade_info {
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unsigned short nr_posible_cpus;
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unsigned short nr_online_cpus;
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unsigned short nasid;
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};
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struct uv_blade_info *uv_blade_info;
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extern short *uv_node_to_blade;
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extern short *uv_cpu_to_blade;
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extern short uv_possible_blades;
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/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
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static inline int uv_blade_processor_id(void)
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{
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return uv_hub_info->blade_processor_id;
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}
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/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
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static inline int uv_numa_blade_id(void)
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{
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return uv_hub_info->numa_blade_id;
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}
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/* Convert a cpu number to the the UV blade number */
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static inline int uv_cpu_to_blade_id(int cpu)
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{
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return uv_cpu_to_blade[cpu];
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}
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/* Convert linux node number to the UV blade number */
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static inline int uv_node_to_blade_id(int nid)
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{
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return uv_node_to_blade[nid];
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}
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/* Convert a blade id to the NASID of the blade */
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static inline int uv_blade_to_nasid(int bid)
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{
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return uv_blade_info[bid].nasid;
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}
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/* Determine the number of possible cpus on a blade */
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static inline int uv_blade_nr_possible_cpus(int bid)
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{
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return uv_blade_info[bid].nr_posible_cpus;
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}
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/* Determine the number of online cpus on a blade */
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static inline int uv_blade_nr_online_cpus(int bid)
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{
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return uv_blade_info[bid].nr_online_cpus;
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}
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/* Convert a cpu id to the NASID of the blade containing the cpu */
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static inline int uv_cpu_to_nasid(int cpu)
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{
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return uv_blade_info[uv_cpu_to_blade_id(cpu)].nasid;
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}
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/* Convert a node number to the NASID of the blade */
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static inline int uv_node_to_nasid(int nid)
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{
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return uv_blade_info[uv_node_to_blade_id(nid)].nasid;
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}
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/* Maximum possible number of blades */
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static inline int uv_num_possible_blades(void)
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{
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return uv_possible_blades;
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}
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#endif /* __ASM_X86_UV_HUB__ */
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