259 lines
9.5 KiB
C
259 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PCI Endpoint *Controller* (EPC) header file
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#ifndef __LINUX_PCI_EPC_H
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#define __LINUX_PCI_EPC_H
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#include <linux/pci-epf.h>
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struct pci_epc;
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enum pci_epc_interface_type {
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UNKNOWN_INTERFACE = -1,
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PRIMARY_INTERFACE,
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SECONDARY_INTERFACE,
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};
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enum pci_epc_irq_type {
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PCI_EPC_IRQ_UNKNOWN,
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PCI_EPC_IRQ_LEGACY,
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PCI_EPC_IRQ_MSI,
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PCI_EPC_IRQ_MSIX,
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};
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static inline const char *
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pci_epc_interface_string(enum pci_epc_interface_type type)
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{
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switch (type) {
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case PRIMARY_INTERFACE:
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return "primary";
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case SECONDARY_INTERFACE:
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return "secondary";
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default:
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return "UNKNOWN interface";
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}
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}
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/**
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* struct pci_epc_ops - set of function pointers for performing EPC operations
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* @write_header: ops to populate configuration space header
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* @set_bar: ops to configure the BAR
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* @clear_bar: ops to reset the BAR
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* @map_addr: ops to map CPU address to PCI address
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* @unmap_addr: ops to unmap CPU address and PCI address
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* @set_msi: ops to set the requested number of MSI interrupts in the MSI
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* capability register
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* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
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* the MSI capability register
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* @set_msix: ops to set the requested number of MSI-X interrupts in the
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* MSI-X capability register
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* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
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* from the MSI-X capability register
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* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
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* @map_msi_irq: ops to map physical address to MSI address and return MSI data
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* @start: ops to start the PCI link
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* @stop: ops to stop the PCI link
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* @get_features: ops to get the features supported by the EPC
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* @owner: the module owner containing the ops
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*/
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struct pci_epc_ops {
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int (*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_header *hdr);
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int (*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t addr, u64 pci_addr, size_t size);
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void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t addr);
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int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u8 interrupts);
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int (*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int (*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u16 interrupts, enum pci_barno, u32 offset);
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int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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enum pci_epc_irq_type type, u16 interrupt_num);
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int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr, u8 interrupt_num,
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u32 entry_size, u32 *msi_data,
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u32 *msi_addr_offset);
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int (*start)(struct pci_epc *epc);
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void (*stop)(struct pci_epc *epc);
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const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
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u8 func_no, u8 vfunc_no);
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struct module *owner;
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};
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/**
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* struct pci_epc_mem_window - address window of the endpoint controller
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* @phys_base: physical base address of the PCI address window
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* @size: the size of the PCI address window
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* @page_size: size of each page
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*/
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struct pci_epc_mem_window {
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phys_addr_t phys_base;
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size_t size;
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size_t page_size;
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};
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/**
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* struct pci_epc_mem - address space of the endpoint controller
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* @window: address window of the endpoint controller
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* @bitmap: bitmap to manage the PCI address space
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* @pages: number of bits representing the address region
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* @lock: mutex to protect bitmap
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*/
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struct pci_epc_mem {
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struct pci_epc_mem_window window;
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unsigned long *bitmap;
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int pages;
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/* mutex to protect against concurrent access for memory allocation*/
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struct mutex lock;
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};
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/**
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* struct pci_epc - represents the PCI EPC device
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* @dev: PCI EPC device
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* @pci_epf: list of endpoint functions present in this EPC device
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* @ops: function pointers for performing endpoint operations
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* @windows: array of address space of the endpoint controller
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* @mem: first window of the endpoint controller, which corresponds to
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* default address space of the endpoint controller supporting
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* single window.
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* @num_windows: number of windows supported by device
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* @max_functions: max number of functions that can be configured in this EPC
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* @max_vfs: Array indicating the maximum number of virtual functions that can
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* be associated with each physical function
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* @group: configfs group representing the PCI EPC device
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* @lock: mutex to protect pci_epc ops
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* @function_num_map: bitmap to manage physical function number
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* @notifier: used to notify EPF of any EPC events (like linkup)
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*/
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struct pci_epc {
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struct device dev;
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struct list_head pci_epf;
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const struct pci_epc_ops *ops;
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struct pci_epc_mem **windows;
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struct pci_epc_mem *mem;
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unsigned int num_windows;
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u8 max_functions;
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u8 *max_vfs;
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struct config_group *group;
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/* mutex to protect against concurrent access of EP controller */
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struct mutex lock;
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unsigned long function_num_map;
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struct atomic_notifier_head notifier;
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};
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/**
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* struct pci_epc_features - features supported by a EPC device per function
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* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
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* @core_init_notifier: indicate cores that can notify about their availability
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* for initialization
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* @msi_capable: indicate if the endpoint function has MSI capability
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* @msix_capable: indicate if the endpoint function has MSI-X capability
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* @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
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* @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
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* @bar_fixed_size: Array specifying the size supported by each BAR
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* @align: alignment size required for BAR buffer allocation
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*/
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struct pci_epc_features {
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unsigned int linkup_notifier : 1;
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unsigned int core_init_notifier : 1;
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unsigned int msi_capable : 1;
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unsigned int msix_capable : 1;
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u8 reserved_bar;
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u8 bar_fixed_64bit;
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u64 bar_fixed_size[PCI_STD_NUM_BARS];
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size_t align;
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};
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#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
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#define pci_epc_create(dev, ops) \
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__pci_epc_create((dev), (ops), THIS_MODULE)
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#define devm_pci_epc_create(dev, ops) \
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__devm_pci_epc_create((dev), (ops), THIS_MODULE)
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static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
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{
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dev_set_drvdata(&epc->dev, data);
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}
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static inline void *epc_get_drvdata(struct pci_epc *epc)
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{
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return dev_get_drvdata(&epc->dev);
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}
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static inline int
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pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb)
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{
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return atomic_notifier_chain_register(&epc->notifier, nb);
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}
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struct pci_epc *
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__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
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struct module *owner);
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struct pci_epc *
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__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
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struct module *owner);
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void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
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void pci_epc_destroy(struct pci_epc *epc);
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int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
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enum pci_epc_interface_type type);
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void pci_epc_linkup(struct pci_epc *epc);
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void pci_epc_init_notify(struct pci_epc *epc);
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void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
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enum pci_epc_interface_type type);
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int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_header *hdr);
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int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr,
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u64 pci_addr, size_t size);
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void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr);
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int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u8 interrupts);
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int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u16 interrupts, enum pci_barno, u32 offset);
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int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr, u8 interrupt_num,
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u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
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int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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enum pci_epc_irq_type type, u16 interrupt_num);
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int pci_epc_start(struct pci_epc *epc);
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void pci_epc_stop(struct pci_epc *epc);
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const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
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u8 func_no, u8 vfunc_no);
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enum pci_barno
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pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
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enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
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*epc_features, enum pci_barno bar);
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struct pci_epc *pci_epc_get(const char *epc_name);
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void pci_epc_put(struct pci_epc *epc);
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int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
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size_t size, size_t page_size);
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int pci_epc_multi_mem_init(struct pci_epc *epc,
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struct pci_epc_mem_window *window,
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unsigned int num_windows);
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void pci_epc_mem_exit(struct pci_epc *epc);
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void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
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phys_addr_t *phys_addr, size_t size);
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void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
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void __iomem *virt_addr, size_t size);
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#endif /* __LINUX_PCI_EPC_H */
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