258 lines
6.8 KiB
C
258 lines
6.8 KiB
C
/*
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* Support for 'media5200-platform' compatible boards.
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*
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* Copyright (C) 2008 Secret Lab Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Description:
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* This code implements support for the Freescape Media5200 platform
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* (built around the MPC5200 SoC).
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*
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* Notable characteristic of the Media5200 is the presence of an FPGA
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* that has all external IRQ lines routed through it. This file implements
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* a cascaded interrupt controller driver which attaches itself to the
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* Virtual IRQ subsystem after the primary mpc5200 interrupt controller
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* is initialized.
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*
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*/
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/time.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/mpc52xx.h>
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static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-gpio", },
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{ .compatible = "mpc5200-gpio", },
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{}
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};
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/* FPGA register set */
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#define MEDIA5200_IRQ_ENABLE (0x40c)
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#define MEDIA5200_IRQ_STATUS (0x410)
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#define MEDIA5200_NUM_IRQS (6)
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#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
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struct media5200_irq {
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void __iomem *regs;
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spinlock_t lock;
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struct irq_domain *irqhost;
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};
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struct media5200_irq media5200_irq;
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static void media5200_irq_unmask(struct irq_data *d)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&media5200_irq.lock, flags);
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val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
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val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
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out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
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spin_unlock_irqrestore(&media5200_irq.lock, flags);
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}
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static void media5200_irq_mask(struct irq_data *d)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&media5200_irq.lock, flags);
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val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
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val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
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out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
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spin_unlock_irqrestore(&media5200_irq.lock, flags);
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}
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static struct irq_chip media5200_irq_chip = {
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.name = "Media5200 FPGA",
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.irq_unmask = media5200_irq_unmask,
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.irq_mask = media5200_irq_mask,
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.irq_mask_ack = media5200_irq_mask,
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};
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void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int sub_virq, val;
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u32 status, enable;
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/* Mask off the cascaded IRQ */
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raw_spin_lock(&desc->lock);
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chip->irq_mask(&desc->irq_data);
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raw_spin_unlock(&desc->lock);
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/* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
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* are pending. 'ffs()' is 1 based */
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status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
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enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
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val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
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if (val) {
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sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
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/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
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* __func__, virq, status, enable, val - 1, sub_virq);
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*/
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generic_handle_irq(sub_virq);
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}
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/* Processing done; can reenable the cascade now */
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raw_spin_lock(&desc->lock);
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chip->irq_ack(&desc->irq_data);
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if (!irqd_irq_disabled(&desc->irq_data))
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chip->irq_unmask(&desc->irq_data);
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raw_spin_unlock(&desc->lock);
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}
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static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
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irq_set_chip_data(virq, &media5200_irq);
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irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
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irq_set_status_flags(virq, IRQ_LEVEL);
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return 0;
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}
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static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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if (intsize != 2)
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return -1;
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pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
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*out_hwirq = intspec[1];
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*out_flags = IRQ_TYPE_NONE;
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return 0;
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}
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static const struct irq_domain_ops media5200_irq_ops = {
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.map = media5200_irq_map,
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.xlate = media5200_irq_xlate,
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};
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/*
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* Setup Media5200 IRQ mapping
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*/
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static void __init media5200_init_irq(void)
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{
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struct device_node *fpga_np;
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int cascade_virq;
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/* First setup the regular MPC5200 interrupt controller */
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mpc52xx_init_irq();
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/* Now find the FPGA IRQ */
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fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
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if (!fpga_np)
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goto out;
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pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
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media5200_irq.regs = of_iomap(fpga_np, 0);
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if (!media5200_irq.regs)
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goto out;
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pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
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cascade_virq = irq_of_parse_and_map(fpga_np, 0);
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if (!cascade_virq)
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goto out;
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pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
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/* Disable all FPGA IRQs */
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out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
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spin_lock_init(&media5200_irq.lock);
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media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
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MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
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if (!media5200_irq.irqhost)
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goto out;
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pr_debug("%s: allocated irqhost\n", __func__);
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irq_set_handler_data(cascade_virq, &media5200_irq);
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irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
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return;
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out:
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pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
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}
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/*
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* Setup the architecture
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*/
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static void __init media5200_setup_arch(void)
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{
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struct device_node *np;
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struct mpc52xx_gpio __iomem *gpio;
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u32 port_config;
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if (ppc_md.progress)
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ppc_md.progress("media5200_setup_arch()", 0);
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/* Map important registers from the internal memory map */
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mpc52xx_map_common_devices();
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/* Some mpc5200 & mpc5200b related configuration */
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mpc5200_setup_xlb_arbiter();
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mpc52xx_setup_pci();
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np = of_find_matching_node(NULL, mpc5200_gpio_ids);
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gpio = of_iomap(np, 0);
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of_node_put(np);
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if (!gpio) {
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printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
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__func__);
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return;
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}
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/* Set port config */
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port_config = in_be32(&gpio->port_config);
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port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
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port_config |= 0x01000000;
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out_be32(&gpio->port_config, port_config);
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/* Unmap zone */
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iounmap(gpio);
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}
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/* list of the supported boards */
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static const char * const board[] __initconst = {
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"fsl,media5200",
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NULL
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};
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init media5200_probe(void)
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{
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return of_flat_dt_match(of_get_flat_dt_root(), board);
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}
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define_machine(media5200_platform) {
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.name = "media5200-platform",
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.probe = media5200_probe,
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.setup_arch = media5200_setup_arch,
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.init = mpc52xx_declare_of_platform_devices,
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.init_IRQ = media5200_init_irq,
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.get_irq = mpc52xx_get_irq,
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.restart = mpc52xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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};
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