354 lines
9.5 KiB
C
354 lines
9.5 KiB
C
#ifndef _ASM_X86_MMU_CONTEXT_H
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#define _ASM_X86_MMU_CONTEXT_H
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#include <asm/desc.h>
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#include <linux/atomic.h>
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#include <linux/mm_types.h>
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#include <trace/events/tlb.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/paravirt.h>
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#include <asm/mpx.h>
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#ifndef CONFIG_PARAVIRT
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static inline void paravirt_activate_mm(struct mm_struct *prev,
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struct mm_struct *next)
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{
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}
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#endif /* !CONFIG_PARAVIRT */
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#ifdef CONFIG_PERF_EVENTS
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extern struct static_key rdpmc_always_available;
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static inline void load_mm_cr4(struct mm_struct *mm)
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{
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if (static_key_false(&rdpmc_always_available) ||
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atomic_read(&mm->context.perf_rdpmc_allowed))
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cr4_set_bits(X86_CR4_PCE);
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else
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cr4_clear_bits(X86_CR4_PCE);
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}
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#else
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static inline void load_mm_cr4(struct mm_struct *mm) {}
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#endif
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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/*
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* ldt_structs can be allocated, used, and freed, but they are never
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* modified while live.
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*/
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struct ldt_struct {
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/*
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* Xen requires page-aligned LDTs with special permissions. This is
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* needed to prevent us from installing evil descriptors such as
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* call gates. On native, we could merge the ldt_struct and LDT
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* allocations, but it's not worth trying to optimize.
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*/
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struct desc_struct *entries;
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int size;
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};
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/*
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* Used for LDT copy/destruction.
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*/
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int init_new_context_ldt(struct task_struct *tsk, struct mm_struct *mm);
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void destroy_context_ldt(struct mm_struct *mm);
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#else /* CONFIG_MODIFY_LDT_SYSCALL */
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static inline int init_new_context_ldt(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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return 0;
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}
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static inline void destroy_context_ldt(struct mm_struct *mm) {}
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#endif
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static inline void load_mm_ldt(struct mm_struct *mm)
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{
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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struct ldt_struct *ldt;
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/* lockless_dereference synchronizes with smp_store_release */
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ldt = lockless_dereference(mm->context.ldt);
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/*
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* Any change to mm->context.ldt is followed by an IPI to all
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* CPUs with the mm active. The LDT will not be freed until
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* after the IPI is handled by all such CPUs. This means that,
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* if the ldt_struct changes before we return, the values we see
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* will be safe, and the new values will be loaded before we run
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* any user code.
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*
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* NB: don't try to convert this to use RCU without extreme care.
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* We would still need IRQs off, because we don't want to change
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* the local LDT after an IPI loaded a newer value than the one
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* that we can see.
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*/
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if (unlikely(ldt))
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set_ldt(ldt->entries, ldt->size);
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else
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clear_LDT();
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#else
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clear_LDT();
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#endif
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DEBUG_LOCKS_WARN_ON(preemptible());
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}
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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#ifdef CONFIG_SMP
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if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_LAZY);
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#endif
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}
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static inline int init_new_context(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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init_new_context_ldt(tsk, mm);
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return 0;
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}
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static inline void destroy_context(struct mm_struct *mm)
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{
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destroy_context_ldt(mm);
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned cpu = smp_processor_id();
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if (likely(prev != next)) {
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#ifdef CONFIG_SMP
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
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this_cpu_write(cpu_tlbstate.active_mm, next);
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#endif
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* Re-load page tables.
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*
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* This logic has an ordering constraint:
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*
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* CPU 0: Write to a PTE for 'next'
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* CPU 0: load bit 1 in mm_cpumask. if nonzero, send IPI.
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* CPU 1: set bit 1 in next's mm_cpumask
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* CPU 1: load from the PTE that CPU 0 writes (implicit)
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*
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* We need to prevent an outcome in which CPU 1 observes
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* the new PTE value and CPU 0 observes bit 1 clear in
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* mm_cpumask. (If that occurs, then the IPI will never
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* be sent, and CPU 0's TLB will contain a stale entry.)
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*
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* The bad outcome can occur if either CPU's load is
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* reordered before that CPU's store, so both CPUs must
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* execute full barriers to prevent this from happening.
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*
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* Thus, switch_mm needs a full barrier between the
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* store to mm_cpumask and any operation that could load
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* from next->pgd. TLB fills are special and can happen
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* due to instruction fetches or for no reason at all,
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* and neither LOCK nor MFENCE orders them.
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* Fortunately, load_cr3() is serializing and gives the
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* ordering guarantee we need.
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*
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*/
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load_cr3(next->pgd);
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trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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/* Stop flush ipis for the previous mm */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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/* Load per-mm CR4 state */
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load_mm_cr4(next);
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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/*
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* Load the LDT, if the LDT is different.
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*
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* It's possible that prev->context.ldt doesn't match
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* the LDT register. This can happen if leave_mm(prev)
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* was called and then modify_ldt changed
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* prev->context.ldt but suppressed an IPI to this CPU.
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* In this case, prev->context.ldt != NULL, because we
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* never set context.ldt to NULL while the mm still
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* exists. That means that next->context.ldt !=
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* prev->context.ldt, because mms never share an LDT.
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*/
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if (unlikely(prev->context.ldt != next->context.ldt))
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load_mm_ldt(next);
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#endif
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}
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#ifdef CONFIG_SMP
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else {
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
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BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next);
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if (!cpumask_test_cpu(cpu, mm_cpumask(next))) {
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/*
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* On established mms, the mm_cpumask is only changed
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* from irq context, from ptep_clear_flush() while in
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* lazy tlb mode, and here. Irqs are blocked during
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* schedule, protecting us from simultaneous changes.
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*/
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* We were in lazy tlb mode and leave_mm disabled
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* tlb flush IPI delivery. We must reload CR3
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* to make sure to use no freed page tables.
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*
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* As above, load_cr3() is serializing and orders TLB
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* fills with respect to the mm_cpumask write.
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*/
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load_cr3(next->pgd);
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trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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load_mm_cr4(next);
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load_mm_ldt(next);
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}
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}
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#endif
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}
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#define activate_mm(prev, next) \
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do { \
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paravirt_activate_mm((prev), (next)); \
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switch_mm((prev), (next), NULL); \
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} while (0);
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#ifdef CONFIG_X86_32
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#define deactivate_mm(tsk, mm) \
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do { \
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lazy_load_gs(0); \
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} while (0)
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#else
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#define deactivate_mm(tsk, mm) \
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do { \
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load_gs_index(0); \
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loadsegment(fs, 0); \
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} while (0)
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#endif
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static inline void arch_dup_mmap(struct mm_struct *oldmm,
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struct mm_struct *mm)
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{
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paravirt_arch_dup_mmap(oldmm, mm);
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}
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static inline void arch_exit_mmap(struct mm_struct *mm)
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{
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paravirt_arch_exit_mmap(mm);
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}
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#ifdef CONFIG_X86_64
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static inline bool is_64bit_mm(struct mm_struct *mm)
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{
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return !config_enabled(CONFIG_IA32_EMULATION) ||
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!(mm->context.ia32_compat == TIF_IA32);
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}
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#else
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static inline bool is_64bit_mm(struct mm_struct *mm)
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{
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return false;
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}
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#endif
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static inline void arch_bprm_mm_init(struct mm_struct *mm,
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struct vm_area_struct *vma)
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{
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mpx_mm_init(mm);
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}
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static inline void arch_unmap(struct mm_struct *mm, struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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/*
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* mpx_notify_unmap() goes and reads a rarely-hot
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* cacheline in the mm_struct. That can be expensive
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* enough to be seen in profiles.
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*
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* The mpx_notify_unmap() call and its contents have been
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* observed to affect munmap() performance on hardware
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* where MPX is not present.
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*
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* The unlikely() optimizes for the fast case: no MPX
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* in the CPU, or no MPX use in the process. Even if
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* we get this wrong (in the unlikely event that MPX
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* is widely enabled on some system) the overhead of
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* MPX itself (reading bounds tables) is expected to
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* overwhelm the overhead of getting this unlikely()
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* consistently wrong.
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*/
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if (unlikely(cpu_feature_enabled(X86_FEATURE_MPX)))
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mpx_notify_unmap(mm, vma, start, end);
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}
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static inline int vma_pkey(struct vm_area_struct *vma)
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{
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u16 pkey = 0;
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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unsigned long vma_pkey_mask = VM_PKEY_BIT0 | VM_PKEY_BIT1 |
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VM_PKEY_BIT2 | VM_PKEY_BIT3;
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pkey = (vma->vm_flags & vma_pkey_mask) >> VM_PKEY_SHIFT;
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#endif
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return pkey;
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}
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static inline bool __pkru_allows_pkey(u16 pkey, bool write)
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{
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u32 pkru = read_pkru();
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if (!__pkru_allows_read(pkru, pkey))
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return false;
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if (write && !__pkru_allows_write(pkru, pkey))
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return false;
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return true;
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}
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/*
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* We only want to enforce protection keys on the current process
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* because we effectively have no access to PKRU for other
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* processes or any way to tell *which * PKRU in a threaded
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* process we could use.
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*
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* So do not enforce things if the VMA is not from the current
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* mm, or if we are in a kernel thread.
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*/
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static inline bool vma_is_foreign(struct vm_area_struct *vma)
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{
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if (!current->mm)
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return true;
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/*
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* Should PKRU be enforced on the access to this VMA? If
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* the VMA is from another process, then PKRU has no
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* relevance and should not be enforced.
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*/
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if (current->mm != vma->vm_mm)
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return true;
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return false;
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}
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static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
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bool write, bool execute, bool foreign)
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{
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/* pkeys never affect instruction fetches */
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if (execute)
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return true;
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/* allow access if the VMA is not one from this process */
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if (foreign || vma_is_foreign(vma))
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return true;
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return __pkru_allows_pkey(vma_pkey(vma), write);
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}
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static inline bool arch_pte_access_permitted(pte_t pte, bool write)
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{
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return __pkru_allows_pkey(pte_flags_pkey(pte_flags(pte)), write);
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}
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#endif /* _ASM_X86_MMU_CONTEXT_H */
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