145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
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* Copyright (C) 2015 John Crispin <john@phrozen.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <linux/memblock.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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#include <asm/mips-cps.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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#include "common.h"
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static void *detect_magic __initdata = detect_memory_region;
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phys_addr_t mips_cpc_default_phys_base(void)
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{
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panic("Cannot detect cpc address");
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}
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static void __init mt7621_memory_detect(void)
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{
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void *dm = &detect_magic;
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phys_addr_t size;
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for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
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if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
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break;
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}
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if ((size == 256 * SZ_1M) &&
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(CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
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__builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
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memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
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memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
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} else {
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memblock_add(MT7621_LOWMEM_BASE, size);
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}
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
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rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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}
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static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
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{
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return;
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soc_dev_attr->soc_id = "mt7621";
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soc_dev_attr->family = "Ralink";
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if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
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(rev & CHIP_REV_ECO_MASK) == 1)
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soc_dev_attr->revision = "E2";
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else
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soc_dev_attr->revision = "E1";
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soc_dev_attr->data = soc_info;
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr);
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return;
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}
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}
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void __init prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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unsigned char *name = NULL;
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u32 n0;
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u32 n1;
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u32 rev;
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/* Early detection of CMP support */
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mips_cm_probe();
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mips_cpc_probe();
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if (mips_cps_numiocu(0)) {
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/*
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* mips_cm_probe() wipes out bootloader
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* config for CM regions and we have to configure them
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* again. This SoC cannot talk to pamlbus devices
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* witout proper iocu region set up.
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*
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* FIXME: it would be better to do this with values
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* from DT, but we need this very early because
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* without this we cannot talk to pretty much anything
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* including serial.
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*/
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write_gcr_reg0_base(MT7621_PALMBUS_BASE);
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write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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__sync();
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}
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
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name = "MT7621";
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soc_info->compatible = "mediatek,mt7621-soc";
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} else {
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panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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}
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ralink_soc = MT762X_SOC_MT7621AT;
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rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"MediaTek %s ver:%u eco:%u",
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name,
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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soc_info->mem_detect = mt7621_memory_detect;
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soc_dev_init(soc_info, rev);
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if (!register_cps_smp_ops())
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return;
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if (!register_cmp_smp_ops())
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return;
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if (!register_vsmp_smp_ops())
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return;
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}
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