Peter De Schrijver dba4072a4a clk: tegra: Refactor PLL programming code ... Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>		2013-04-04 16:10:33 -06:00
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Makefile	clk: tegra: add clock support for Tegra30	2013-01-28 11:19:07 -07:00
clk-audio-sync.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-divider.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-periph-gate.c	clk: tegra: Fix periph_clk_to_bit macro	2013-04-04 16:08:27 -06:00
clk-periph.c	clk: tegra: Export peripheral reset functions	2013-04-04 16:08:31 -06:00
clk-pll-out.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-pll.c	clk: tegra: Refactor PLL programming code	2013-04-04 16:10:33 -06:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: tegra: Refactor PLL programming code	2013-04-04 16:10:33 -06:00
clk-tegra30.c	clk: tegra: Refactor PLL programming code	2013-04-04 16:10:33 -06:00
clk.c	clk: tegra: provide dummy cpu car ops	2013-04-04 16:10:12 -06:00
clk.h	clk: tegra: Refactor PLL programming code	2013-04-04 16:10:33 -06:00