465 lines
11 KiB
C
465 lines
11 KiB
C
/*
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* Driver for Amlogic Meson SPI flash controller (SPIFC)
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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/* register map */
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#define REG_CMD 0x00
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#define REG_ADDR 0x04
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#define REG_CTRL 0x08
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#define REG_CTRL1 0x0c
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#define REG_STATUS 0x10
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#define REG_CTRL2 0x14
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#define REG_CLOCK 0x18
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#define REG_USER 0x1c
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#define REG_USER1 0x20
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#define REG_USER2 0x24
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#define REG_USER3 0x28
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#define REG_USER4 0x2c
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#define REG_SLAVE 0x30
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#define REG_SLAVE1 0x34
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#define REG_SLAVE2 0x38
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#define REG_SLAVE3 0x3c
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#define REG_C0 0x40
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#define REG_B8 0x60
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#define REG_MAX 0x7c
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/* register fields */
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#define CMD_USER BIT(18)
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#define CTRL_ENABLE_AHB BIT(17)
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#define CLOCK_SOURCE BIT(31)
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#define CLOCK_DIV_SHIFT 12
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#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
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#define CLOCK_CNT_HIGH_SHIFT 6
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#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
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#define CLOCK_CNT_LOW_SHIFT 0
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#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
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#define USER_DIN_EN_MS BIT(0)
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#define USER_CMP_MODE BIT(2)
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#define USER_UC_DOUT_SEL BIT(27)
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#define USER_UC_DIN_SEL BIT(28)
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#define USER_UC_MASK ((BIT(5) - 1) << 27)
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#define USER1_BN_UC_DOUT_SHIFT 17
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#define USER1_BN_UC_DOUT_MASK (0xff << 16)
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#define USER1_BN_UC_DIN_SHIFT 8
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#define USER1_BN_UC_DIN_MASK (0xff << 8)
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#define USER4_CS_ACT BIT(30)
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#define SLAVE_TRST_DONE BIT(4)
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#define SLAVE_OP_MODE BIT(30)
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#define SLAVE_SW_RST BIT(31)
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#define SPIFC_BUFFER_SIZE 64
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/**
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* struct meson_spifc
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* @master: the SPI master
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* @regmap: regmap for device registers
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* @clk: input clock of the built-in baud rate generator
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* @device: the device structure
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*/
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struct meson_spifc {
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struct spi_master *master;
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struct regmap *regmap;
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struct clk *clk;
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struct device *dev;
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};
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static const struct regmap_config spifc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = REG_MAX,
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};
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/**
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* meson_spifc_wait_ready() - wait for the current operation to terminate
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* @spifc: the Meson SPI device
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* Return: 0 on success, a negative value on error
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*/
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static int meson_spifc_wait_ready(struct meson_spifc *spifc)
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{
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unsigned long deadline = jiffies + msecs_to_jiffies(5);
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u32 data;
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do {
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regmap_read(spifc->regmap, REG_SLAVE, &data);
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if (data & SLAVE_TRST_DONE)
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return 0;
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cond_resched();
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} while (!time_after(jiffies, deadline));
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return -ETIMEDOUT;
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}
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/**
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* meson_spifc_drain_buffer() - copy data from device buffer to memory
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* @spifc: the Meson SPI device
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* @buf: the destination buffer
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* @len: number of bytes to copy
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*/
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static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf,
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int len)
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{
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u32 data;
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int i = 0;
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while (i < len) {
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regmap_read(spifc->regmap, REG_C0 + i, &data);
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if (len - i >= 4) {
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*((u32 *)buf) = data;
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buf += 4;
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} else {
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memcpy(buf, &data, len - i);
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break;
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}
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i += 4;
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}
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}
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/**
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* meson_spifc_fill_buffer() - copy data from memory to device buffer
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* @spifc: the Meson SPI device
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* @buf: the source buffer
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* @len: number of bytes to copy
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*/
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static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf,
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int len)
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{
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u32 data;
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int i = 0;
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while (i < len) {
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if (len - i >= 4)
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data = *(u32 *)buf;
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else
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memcpy(&data, buf, len - i);
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regmap_write(spifc->regmap, REG_C0 + i, data);
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buf += 4;
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i += 4;
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}
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}
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/**
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* meson_spifc_setup_speed() - program the clock divider
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* @spifc: the Meson SPI device
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* @speed: desired speed in Hz
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*/
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static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed)
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{
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unsigned long parent, value;
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int n;
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parent = clk_get_rate(spifc->clk);
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n = max_t(int, parent / speed - 1, 1);
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dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent,
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speed, n);
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value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK;
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value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK;
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value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) &
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CLOCK_CNT_HIGH_MASK;
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regmap_write(spifc->regmap, REG_CLOCK, value);
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}
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/**
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* meson_spifc_txrx() - transfer a chunk of data
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* @spifc: the Meson SPI device
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* @xfer: the current SPI transfer
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* @offset: offset of the data to transfer
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* @len: length of the data to transfer
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* @last_xfer: whether this is the last transfer of the message
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* @last_chunk: whether this is the last chunk of the transfer
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* Return: 0 on success, a negative value on error
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*/
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static int meson_spifc_txrx(struct meson_spifc *spifc,
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struct spi_transfer *xfer,
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int offset, int len, bool last_xfer,
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bool last_chunk)
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{
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bool keep_cs = true;
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int ret;
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if (xfer->tx_buf)
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meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len);
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/* enable DOUT stage */
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regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
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USER_UC_DOUT_SEL);
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regmap_write(spifc->regmap, REG_USER1,
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(8 * len - 1) << USER1_BN_UC_DOUT_SHIFT);
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/* enable data input during DOUT */
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regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
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USER_DIN_EN_MS);
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if (last_chunk) {
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if (last_xfer)
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keep_cs = xfer->cs_change;
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else
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keep_cs = !xfer->cs_change;
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}
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regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
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keep_cs ? USER4_CS_ACT : 0);
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/* clear transition done bit */
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regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
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/* start transfer */
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regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
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ret = meson_spifc_wait_ready(spifc);
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if (!ret && xfer->rx_buf)
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meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len);
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return ret;
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}
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/**
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* meson_spifc_transfer_one() - perform a single transfer
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* @master: the SPI master
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* @spi: the SPI device
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* @xfer: the current SPI transfer
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* Return: 0 on success, a negative value on error
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*/
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static int meson_spifc_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct meson_spifc *spifc = spi_master_get_devdata(master);
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int len, done = 0, ret = 0;
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meson_spifc_setup_speed(spifc, xfer->speed_hz);
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regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
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while (done < xfer->len && !ret) {
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len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE);
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ret = meson_spifc_txrx(spifc, xfer, done, len,
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spi_transfer_is_last(master, xfer),
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done + len >= xfer->len);
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done += len;
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}
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regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
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CTRL_ENABLE_AHB);
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return ret;
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}
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/**
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* meson_spifc_hw_init() - reset and initialize the SPI controller
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* @spifc: the Meson SPI device
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*/
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static void meson_spifc_hw_init(struct meson_spifc *spifc)
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{
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/* reset device */
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regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
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SLAVE_SW_RST);
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/* disable compatible mode */
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regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
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/* set master mode */
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regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
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}
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static int meson_spifc_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct meson_spifc *spifc;
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struct resource *res;
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void __iomem *base;
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unsigned int rate;
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int ret = 0;
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master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc));
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if (!master)
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return -ENOMEM;
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platform_set_drvdata(pdev, master);
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spifc = spi_master_get_devdata(master);
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spifc->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(spifc->dev, res);
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if (IS_ERR(base)) {
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ret = PTR_ERR(base);
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goto out_err;
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}
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spifc->regmap = devm_regmap_init_mmio(spifc->dev, base,
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&spifc_regmap_config);
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if (IS_ERR(spifc->regmap)) {
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ret = PTR_ERR(spifc->regmap);
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goto out_err;
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}
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spifc->clk = devm_clk_get(spifc->dev, NULL);
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if (IS_ERR(spifc->clk)) {
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dev_err(spifc->dev, "missing clock\n");
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ret = PTR_ERR(spifc->clk);
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goto out_err;
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}
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ret = clk_prepare_enable(spifc->clk);
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if (ret) {
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dev_err(spifc->dev, "can't prepare clock\n");
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goto out_err;
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}
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rate = clk_get_rate(spifc->clk);
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master->num_chipselect = 1;
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master->dev.of_node = pdev->dev.of_node;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->auto_runtime_pm = true;
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master->transfer_one = meson_spifc_transfer_one;
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master->min_speed_hz = rate >> 6;
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master->max_speed_hz = rate >> 1;
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meson_spifc_hw_init(spifc);
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pm_runtime_set_active(spifc->dev);
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pm_runtime_enable(spifc->dev);
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ret = devm_spi_register_master(spifc->dev, master);
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if (ret) {
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dev_err(spifc->dev, "failed to register spi master\n");
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goto out_clk;
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}
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return 0;
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out_clk:
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clk_disable_unprepare(spifc->clk);
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out_err:
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spi_master_put(master);
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return ret;
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}
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static int meson_spifc_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct meson_spifc *spifc = spi_master_get_devdata(master);
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pm_runtime_get_sync(&pdev->dev);
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clk_disable_unprepare(spifc->clk);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int meson_spifc_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct meson_spifc *spifc = spi_master_get_devdata(master);
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int ret;
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ret = spi_master_suspend(master);
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if (ret)
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return ret;
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if (!pm_runtime_suspended(dev))
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clk_disable_unprepare(spifc->clk);
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return 0;
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}
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static int meson_spifc_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct meson_spifc *spifc = spi_master_get_devdata(master);
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int ret;
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if (!pm_runtime_suspended(dev)) {
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ret = clk_prepare_enable(spifc->clk);
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if (ret)
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return ret;
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}
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meson_spifc_hw_init(spifc);
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ret = spi_master_resume(master);
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if (ret)
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clk_disable_unprepare(spifc->clk);
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return ret;
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}
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#endif /* CONFIG_PM_SLEEP */
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#ifdef CONFIG_PM
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static int meson_spifc_runtime_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct meson_spifc *spifc = spi_master_get_devdata(master);
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clk_disable_unprepare(spifc->clk);
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return 0;
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}
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static int meson_spifc_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct meson_spifc *spifc = spi_master_get_devdata(master);
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return clk_prepare_enable(spifc->clk);
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}
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#endif /* CONFIG_PM */
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static const struct dev_pm_ops meson_spifc_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume)
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SET_RUNTIME_PM_OPS(meson_spifc_runtime_suspend,
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meson_spifc_runtime_resume,
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NULL)
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};
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static const struct of_device_id meson_spifc_dt_match[] = {
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{ .compatible = "amlogic,meson6-spifc", },
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{ .compatible = "amlogic,meson-gxbb-spifc", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, meson_spifc_dt_match);
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static struct platform_driver meson_spifc_driver = {
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.probe = meson_spifc_probe,
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.remove = meson_spifc_remove,
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.driver = {
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.name = "meson-spifc",
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.of_match_table = of_match_ptr(meson_spifc_dt_match),
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.pm = &meson_spifc_pm_ops,
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},
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};
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module_platform_driver(meson_spifc_driver);
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MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
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MODULE_DESCRIPTION("Amlogic Meson SPIFC driver");
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MODULE_LICENSE("GPL v2");
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