424 lines
9.2 KiB
C
424 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* CLx support
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*
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* Copyright (C) 2020 - 2023, Intel Corporation
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* Authors: Gil Fine <gil.fine@intel.com>
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* Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#include <linux/module.h>
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#include "tb.h"
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static bool clx_enabled = true;
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module_param_named(clx, clx_enabled, bool, 0444);
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MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");
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static const char *clx_name(unsigned int clx)
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{
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switch (clx) {
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case TB_CL0S | TB_CL1 | TB_CL2:
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return "CL0s/CL1/CL2";
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case TB_CL1 | TB_CL2:
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return "CL1/CL2";
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case TB_CL0S | TB_CL2:
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return "CL0s/CL2";
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case TB_CL0S | TB_CL1:
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return "CL0s/CL1";
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case TB_CL0S:
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return "CL0s";
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case 0:
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return "disabled";
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default:
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return "unknown";
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}
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}
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static int tb_port_pm_secondary_set(struct tb_port *port, bool secondary)
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{
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u32 phy;
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int ret;
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ret = tb_port_read(port, &phy, TB_CFG_PORT,
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port->cap_phy + LANE_ADP_CS_1, 1);
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if (ret)
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return ret;
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if (secondary)
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phy |= LANE_ADP_CS_1_PMS;
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else
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phy &= ~LANE_ADP_CS_1_PMS;
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return tb_port_write(port, &phy, TB_CFG_PORT,
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port->cap_phy + LANE_ADP_CS_1, 1);
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}
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static int tb_port_pm_secondary_enable(struct tb_port *port)
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{
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return tb_port_pm_secondary_set(port, true);
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}
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static int tb_port_pm_secondary_disable(struct tb_port *port)
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{
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return tb_port_pm_secondary_set(port, false);
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}
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/* Called for USB4 or Titan Ridge routers only */
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static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx)
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{
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u32 val, mask = 0;
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bool ret;
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/* Don't enable CLx in case of two single-lane links */
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if (!port->bonded && port->dual_link_port)
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return false;
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/* Don't enable CLx in case of inter-domain link */
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if (port->xdomain)
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return false;
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if (tb_switch_is_usb4(port->sw)) {
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if (!usb4_port_clx_supported(port))
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return false;
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} else if (!tb_lc_is_clx_supported(port)) {
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return false;
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}
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if (clx & TB_CL0S)
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mask |= LANE_ADP_CS_0_CL0S_SUPPORT;
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if (clx & TB_CL1)
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mask |= LANE_ADP_CS_0_CL1_SUPPORT;
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if (clx & TB_CL2)
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mask |= LANE_ADP_CS_0_CL2_SUPPORT;
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ret = tb_port_read(port, &val, TB_CFG_PORT,
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port->cap_phy + LANE_ADP_CS_0, 1);
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if (ret)
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return false;
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return !!(val & mask);
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}
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static int tb_port_clx_set(struct tb_port *port, unsigned int clx, bool enable)
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{
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u32 phy, mask = 0;
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int ret;
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if (clx & TB_CL0S)
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mask |= LANE_ADP_CS_1_CL0S_ENABLE;
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if (clx & TB_CL1)
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mask |= LANE_ADP_CS_1_CL1_ENABLE;
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if (clx & TB_CL2)
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mask |= LANE_ADP_CS_1_CL2_ENABLE;
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if (!mask)
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return -EOPNOTSUPP;
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ret = tb_port_read(port, &phy, TB_CFG_PORT,
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port->cap_phy + LANE_ADP_CS_1, 1);
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if (ret)
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return ret;
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if (enable)
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phy |= mask;
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else
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phy &= ~mask;
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return tb_port_write(port, &phy, TB_CFG_PORT,
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port->cap_phy + LANE_ADP_CS_1, 1);
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}
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static int tb_port_clx_disable(struct tb_port *port, unsigned int clx)
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{
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return tb_port_clx_set(port, clx, false);
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}
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static int tb_port_clx_enable(struct tb_port *port, unsigned int clx)
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{
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return tb_port_clx_set(port, clx, true);
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}
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static int tb_port_clx(struct tb_port *port)
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{
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u32 val;
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int ret;
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if (!tb_port_clx_supported(port, TB_CL0S | TB_CL1 | TB_CL2))
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return 0;
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ret = tb_port_read(port, &val, TB_CFG_PORT,
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port->cap_phy + LANE_ADP_CS_1, 1);
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if (ret)
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return ret;
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if (val & LANE_ADP_CS_1_CL0S_ENABLE)
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ret |= TB_CL0S;
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if (val & LANE_ADP_CS_1_CL1_ENABLE)
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ret |= TB_CL1;
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if (val & LANE_ADP_CS_1_CL2_ENABLE)
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ret |= TB_CL2;
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return ret;
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}
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/**
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* tb_port_clx_is_enabled() - Is given CL state enabled
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* @port: USB4 port to check
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* @clx: Mask of CL states to check
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*
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* Returns true if any of the given CL states is enabled for @port.
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*/
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bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx)
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{
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return !!(tb_port_clx(port) & clx);
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}
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/**
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* tb_switch_clx_init() - Initialize router CL states
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* @sw: Router
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*
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* Can be called for any router. Initializes the current CL state by
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* reading it from the hardware.
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*
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* Returns %0 in case of success and negative errno in case of failure.
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*/
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int tb_switch_clx_init(struct tb_switch *sw)
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{
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struct tb_port *up, *down;
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unsigned int clx, tmp;
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if (tb_switch_is_icm(sw))
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return 0;
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if (!tb_route(sw))
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return 0;
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if (!tb_switch_clx_is_supported(sw))
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return 0;
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up = tb_upstream_port(sw);
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down = tb_switch_downstream_port(sw);
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clx = tb_port_clx(up);
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tmp = tb_port_clx(down);
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if (clx != tmp)
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tb_sw_warn(sw, "CLx: inconsistent configuration %#x != %#x\n",
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clx, tmp);
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tb_sw_dbg(sw, "CLx: current mode: %s\n", clx_name(clx));
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sw->clx = clx;
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return 0;
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}
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static int tb_switch_pm_secondary_resolve(struct tb_switch *sw)
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{
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struct tb_port *up, *down;
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int ret;
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if (!tb_route(sw))
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return 0;
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up = tb_upstream_port(sw);
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down = tb_switch_downstream_port(sw);
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ret = tb_port_pm_secondary_enable(up);
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if (ret)
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return ret;
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return tb_port_pm_secondary_disable(down);
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}
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static int tb_switch_mask_clx_objections(struct tb_switch *sw)
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{
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int up_port = sw->config.upstream_port_number;
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u32 offset, val[2], mask_obj, unmask_obj;
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int ret, i;
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/* Only Titan Ridge of pre-USB4 devices support CLx states */
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if (!tb_switch_is_titan_ridge(sw))
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return 0;
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if (!tb_route(sw))
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return 0;
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/*
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* In Titan Ridge there are only 2 dual-lane Thunderbolt ports:
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* Port A consists of lane adapters 1,2 and
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* Port B consists of lane adapters 3,4
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* If upstream port is A, (lanes are 1,2), we mask objections from
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* port B (lanes 3,4) and unmask objections from Port A and vice-versa.
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*/
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if (up_port == 1) {
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mask_obj = TB_LOW_PWR_C0_PORT_B_MASK;
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unmask_obj = TB_LOW_PWR_C1_PORT_A_MASK;
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offset = TB_LOW_PWR_C1_CL1;
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} else {
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mask_obj = TB_LOW_PWR_C1_PORT_A_MASK;
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unmask_obj = TB_LOW_PWR_C0_PORT_B_MASK;
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offset = TB_LOW_PWR_C3_CL1;
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}
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->cap_lp + offset, ARRAY_SIZE(val));
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if (ret)
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return ret;
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for (i = 0; i < ARRAY_SIZE(val); i++) {
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val[i] |= mask_obj;
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val[i] &= ~unmask_obj;
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}
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return tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->cap_lp + offset, ARRAY_SIZE(val));
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}
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/**
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* tb_switch_clx_is_supported() - Is CLx supported on this type of router
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* @sw: The router to check CLx support for
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*/
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bool tb_switch_clx_is_supported(const struct tb_switch *sw)
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{
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if (!clx_enabled)
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return false;
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if (sw->quirks & QUIRK_NO_CLX)
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return false;
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/*
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* CLx is not enabled and validated on Intel USB4 platforms
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* before Alder Lake.
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*/
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if (tb_switch_is_tiger_lake(sw))
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return false;
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return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw);
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}
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static bool validate_mask(unsigned int clx)
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{
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/* Previous states need to be enabled */
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if (clx & TB_CL1)
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return (clx & TB_CL0S) == TB_CL0S;
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return true;
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}
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/**
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* tb_switch_clx_enable() - Enable CLx on upstream port of specified router
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* @sw: Router to enable CLx for
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* @clx: The CLx state to enable
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*
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* CLx is enabled only if both sides of the link support CLx, and if both sides
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* of the link are not configured as two single lane links and only if the link
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* is not inter-domain link. The complete set of conditions is described in CM
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* Guide 1.0 section 8.1.
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*
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* Returns %0 on success or an error code on failure.
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*/
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int tb_switch_clx_enable(struct tb_switch *sw, unsigned int clx)
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{
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bool up_clx_support, down_clx_support;
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struct tb_switch *parent_sw;
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struct tb_port *up, *down;
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int ret;
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if (!clx || sw->clx == clx)
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return 0;
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if (!validate_mask(clx))
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return -EINVAL;
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parent_sw = tb_switch_parent(sw);
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if (!parent_sw)
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return 0;
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if (!tb_switch_clx_is_supported(parent_sw) ||
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!tb_switch_clx_is_supported(sw))
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return 0;
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/* Only support CL2 for v2 routers */
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if ((clx & TB_CL2) &&
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(usb4_switch_version(parent_sw) < 2 ||
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usb4_switch_version(sw) < 2))
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return -EOPNOTSUPP;
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ret = tb_switch_pm_secondary_resolve(sw);
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if (ret)
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return ret;
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up = tb_upstream_port(sw);
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down = tb_switch_downstream_port(sw);
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up_clx_support = tb_port_clx_supported(up, clx);
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down_clx_support = tb_port_clx_supported(down, clx);
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tb_port_dbg(up, "CLx: %s %ssupported\n", clx_name(clx),
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up_clx_support ? "" : "not ");
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tb_port_dbg(down, "CLx: %s %ssupported\n", clx_name(clx),
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down_clx_support ? "" : "not ");
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if (!up_clx_support || !down_clx_support)
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return -EOPNOTSUPP;
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ret = tb_port_clx_enable(up, clx);
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if (ret)
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return ret;
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ret = tb_port_clx_enable(down, clx);
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if (ret) {
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tb_port_clx_disable(up, clx);
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return ret;
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}
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ret = tb_switch_mask_clx_objections(sw);
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if (ret) {
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tb_port_clx_disable(up, clx);
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tb_port_clx_disable(down, clx);
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return ret;
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}
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sw->clx |= clx;
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tb_sw_dbg(sw, "CLx: %s enabled\n", clx_name(clx));
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return 0;
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}
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/**
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* tb_switch_clx_disable() - Disable CLx on upstream port of specified router
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* @sw: Router to disable CLx for
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*
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* Disables all CL states of the given router. Can be called on any
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* router and if the states were not enabled already does nothing.
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*
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* Returns the CL states that were disabled or negative errno in case of
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* failure.
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*/
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int tb_switch_clx_disable(struct tb_switch *sw)
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{
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unsigned int clx = sw->clx;
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struct tb_port *up, *down;
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int ret;
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if (!tb_switch_clx_is_supported(sw))
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return 0;
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if (!clx)
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return 0;
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up = tb_upstream_port(sw);
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down = tb_switch_downstream_port(sw);
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ret = tb_port_clx_disable(up, clx);
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if (ret)
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return ret;
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ret = tb_port_clx_disable(down, clx);
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if (ret)
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return ret;
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sw->clx = 0;
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tb_sw_dbg(sw, "CLx: %s disabled\n", clx_name(clx));
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return clx;
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}
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