81 lines
2.3 KiB
C
81 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <linux/gfp.h>
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#include <linux/cache.h>
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#include <linux/dma-map-ops.h>
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#include <linux/iommu.h>
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#include <xen/xen.h>
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#include <asm/cacheflush.h>
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#include <asm/xen/xen-ops.h>
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long start = (unsigned long)phys_to_virt(paddr);
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dcache_clean_poc(start, start + size);
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}
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long start = (unsigned long)phys_to_virt(paddr);
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if (dir == DMA_TO_DEVICE)
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return;
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dcache_inval_poc(start, start + size);
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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unsigned long start = (unsigned long)page_address(page);
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/*
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* The architecture only requires a clean to the PoC here in order to
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* meet the requirements of the DMA API. However, some vendors (i.e.
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* Qualcomm) abuse the DMA API for transferring buffers from the
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* non-secure to the secure world, resetting the system if a non-secure
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* access shows up after the buffer has been transferred:
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*
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* https://lore.kernel.org/r/20221114110329.68413-1-manivannan.sadhasivam@linaro.org
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*
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* Using clean+invalidate appears to make this issue less likely, but
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* the drivers themselves still need fixing as the CPU could issue a
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* speculative read from the buffer via the linear mapping irrespective
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* of the cache maintenance we use. Once the drivers are fixed, we can
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* relax this to a clean operation.
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*/
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dcache_clean_inval_poc(start, start + size);
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}
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#ifdef CONFIG_IOMMU_DMA
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void arch_teardown_dma_ops(struct device *dev)
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{
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dev->dma_ops = NULL;
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}
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#endif
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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int cls = cache_line_size_of_cpu();
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WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
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TAINT_CPU_OUT_OF_SPEC,
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"%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
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dev_driver_string(dev), dev_name(dev),
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ARCH_DMA_MINALIGN, cls);
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dev->dma_coherent = coherent;
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if (iommu)
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iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
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xen_setup_dma_ops(dev);
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}
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