OpenCloudOS-Kernel/include/linux/soc
Linus Torvalds 7ddb58cb0e The usual collection of clk driver updates and new driver additions. In
terms of lines it's mainly Qualcomm and Mediatek code, supporting
 various SoCs and their multitude of clk controllers.
 
 New Drivers:
  - GCC and RPMcc support for Qualcomm QCM2290 SoCs
  - GCC support for Qualcomm MSM8994/MSM8992 SoCs
  - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
  - Support for Mediatek MT8195 SoCs
  - Initial clock driver for the Exynos850 SoC
  - Add i.MX8ULP clock driver and related bindings
 
 Updates:
  - Clock power management for new SAMA7G5 SoC
  - Updates to the master clock driver and sam9x60-pll to be able to use
    cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while
    changing the frequency via DVFS
  - Use ARRAY_SIZE in qcom clk drivers
  - Remove some impractical fallback parent names in qcom clk drivers
  - Make Mediatek clk drivers tristate
  - Refactoring of the CPU clock code and conversion of Samsung Exynos5433
    CPU clock driver to the platform driver
  - A few conversions to devm_platform_ioremap_resource()
  - Updates of the Samsung Kconfig help text
  - Update video path realted clocks for Amlogic meson8
  - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
  - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
  - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
  - Remove unused helpers from i.MX specific clock header
  - Rework all i.MX clk based helpers to use clk_hw based ones
  - Rework i.MX gate/mux/divider wrappers
  - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
  - Update i.MX pllv4 and composite clocks to support i.MX8ULP
  - Disable i.MX7ULP composite clock during initialization
  - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
  - Disable the i.MX pfd when set pfdv2 clock rate
  - Add support for i.MX8ULP in pfdv2
  - Add the pcc reset controller support on i.MX8ULP
  - Fix the build break when clk-imx8ulp is built as module
  - Move csi_sel mux to correct base register in i.MX6UL clock drivr
  - Fix csi clk gate register in i.MX6UL clock driver
  - Fix build bug making CLK_IMX8ULP select MXC_CLK
  - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
  - Add Ethernet clocks on Renesas RZ/G2L
  - Move Rockchip to use module_platform_probe
  - Enable usage of Coresight related clocks on Rockchip rk3399
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmGDLIwRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSWasBAA2TTYnSNm/vaNHYPrKRhv5OgALOX5T8yy
 rylvO8qcGrmzX3lVRiO4Bp34jZxQQMG7d2eJn6OMbGEN+9GcsZGA3p4zA8wZaXkN
 yAnddCUEyFl2zMrikXLijhjJ87bmsKUaHHN+zGrGAxC9/VBMwDUPjp9Gy4kdmUFj
 0fq2yhWULulm7UgDTLzwow22wCYYx9/SaNbhnDj7s/eV5N2oexXOrwfIlDHtXnMZ
 4zbJtZ4GKmdicUUMIVzO7wrdEHcWgbPrY2S8UuUbM5PPMzsX7OZ4k/w94p18iT40
 kaJnvEgwZomsYkBMMTrxRjlI/AU3r9omyquKEPX2UXUsTqGHOXZqFXVDPS/6tnvU
 +sqP1V59NMmN9t3HomZ+gr+VKyjakYXuz7QlZZ5kuZRM0aWDfCaq8UEAjyU1WQ+J
 NI4BKzok7+JqEZ25MjcpEV6UBrzNnJ3SMGGiiEUxL6Fl4BE9anVUn06E16v3b5Vb
 k36eosnT3gCBvhNI6gV5zIUyavwb4ga4QJyRQJBeHE7qSVegeoauS8qTFvV04tud
 fWZwAqdLUU/fVse8iuolciZBMAkiuI/R0N8/rZ3MHLe3VB0D/Q/XWGcIheyVpALK
 KAWQ/OA96mM9qf1VBkeItdciSQ+rwAcivmcJTvVIUiwlNk36CYzRsja+sgcNphPH
 WV1CLOIrOgQ=
 =Is+O
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The usual collection of clk driver updates and new driver additions.
  In terms of lines it's mainly Qualcomm and Mediatek code, supporting
  various SoCs and their multitude of clk controllers.

  New Drivers:
   - GCC and RPMcc support for Qualcomm QCM2290 SoCs
   - GCC support for Qualcomm MSM8994/MSM8992 SoCs
   - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
   - Support for Mediatek MT8195 SoCs
   - Initial clock driver for the Exynos850 SoC
   - Add i.MX8ULP clock driver and related bindings

  Updates:
   - Clock power management for new SAMA7G5 SoC
   - Updates to the master clock driver and sam9x60-pll to be able to
     use cpufreq-dt driver and avoid overclocking of CPU and MCK0
     domains while changing the frequency via DVFS
   - Use ARRAY_SIZE in qcom clk drivers
   - Remove some impractical fallback parent names in qcom clk drivers
   - Make Mediatek clk drivers tristate
   - Refactoring of the CPU clock code and conversion of Samsung
     Exynos5433 CPU clock driver to the platform driver
   - A few conversions to devm_platform_ioremap_resource()
   - Updates of the Samsung Kconfig help text
   - Update video path realted clocks for Amlogic meson8
   - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
   - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
   - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
   - Remove unused helpers from i.MX specific clock header
   - Rework all i.MX clk based helpers to use clk_hw based ones
   - Rework i.MX gate/mux/divider wrappers
   - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
   - Update i.MX pllv4 and composite clocks to support i.MX8ULP
   - Disable i.MX7ULP composite clock during initialization
   - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
   - Disable the i.MX pfd when set pfdv2 clock rate
   - Add support for i.MX8ULP in pfdv2
   - Add the pcc reset controller support on i.MX8ULP
   - Fix the build break when clk-imx8ulp is built as module
   - Move csi_sel mux to correct base register in i.MX6UL clock drivr
   - Fix csi clk gate register in i.MX6UL clock driver
   - Fix build bug making CLK_IMX8ULP select MXC_CLK
   - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
   - Add Ethernet clocks on Renesas RZ/G2L
   - Move Rockchip to use module_platform_probe
   - Enable usage of Coresight related clocks on Rockchip rk3399"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
  clk: use clk_core_get_rate_recalc() in clk_rate_get()
  clk: at91: sama7g5: set low limit for mck0 at 32KHz
  clk: at91: sama7g5: remove prescaler part of master clock
  clk: at91: clk-master: add notifier for divider
  clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
  clk: at91: clk-master: fix prescaler logic
  clk: at91: clk-master: mask mckr against layout->mask
  clk: at91: clk-master: check if div or pres is zero
  clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
  clk: at91: pmc: add sama7g5 to the list of available pmcs
  clk: at91: clk-master: improve readability by using local variables
  clk: at91: clk-master: add register definition for sama7g5's master clock
  clk: at91: sama7g5: add securam's peripheral clock
  clk: at91: pmc: execute suspend/resume only for backup mode
  clk: at91: re-factor clocks suspend/resume
  clk: ux500: Add driver for the reset portions of PRCC
  dt-bindings: clock: u8500: Rewrite in YAML and extend
  clk: composite: Use rate_ops.determine_rate when also a mux is available
  clk: samsung: describe drivers in Kconfig
  clk: samsung: exynos5433: update apollo and atlas clock probing
  ...
2021-11-03 21:18:44 -07:00
..
actions
amlogic drm/meson: drop use of drmP.h 2019-07-17 12:47:57 +02:00
brcmstb soc: bcm: brcmstb: add stubs for getting platform IDs 2021-01-20 12:07:23 -08:00
cirrus ARM: ep93xx: move pinctrl interfaces into include/linux/soc 2019-04-28 23:08:40 -07:00
dove
ixp4xx soc: ixp4xx: move cpu detection to linux/soc/ixp4xx/cpu.h 2021-06-17 15:30:54 +02:00
marvell/octeontx2 marvell: octeontx2: build error: unknown type name 'u64' 2021-10-13 13:25:36 -07:00
mediatek soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 2021-09-13 10:52:12 +02:00
mmp soc: mmp: guard include of asm/cputype.h with CONFIG_ARM{,64} 2019-10-21 19:13:56 -07:00
nxp serial: lpc32xx: allow compile testing 2019-08-15 21:34:02 +02:00
qcom The usual collection of clk driver updates and new driver additions. In 2021-11-03 21:18:44 -07:00
renesas soc: renesas: rcar-sysc: Drop legacy handling 2018-06-18 12:00:29 +02:00
samsung soc: samsung: exynos-chipid: Pass revision reg offsets 2021-10-15 09:48:40 +02:00
sunxi
ti soc: ti: k3-ringacc: add AM64 DMA rings support. 2020-12-11 21:20:09 +05:30