327 lines
9.0 KiB
C
327 lines
9.0 KiB
C
#ifndef _ASM_POWERPC_MMU_H_
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#define _ASM_POWERPC_MMU_H_
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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/*
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* MMU features bit definitions
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*/
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/*
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* MMU families
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*/
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#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
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#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
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#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
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#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
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/* Radix page table supported and enabled */
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#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
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/*
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* Individual features below.
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*/
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/*
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* Kernel read only support.
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* We added the ppp value 0b110 in ISA 2.04.
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*/
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#define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
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/*
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* We need to clear top 16bits of va (from the remaining 64 bits )in
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* tlbie* instructions
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*/
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#define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
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/* Enable use of high BAT registers */
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#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
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/* Enable >32-bit physical addresses on 32-bit processor, only used
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* by CONFIG_6xx currently as BookE supports that from day 1
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*/
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#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
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/* Enable use of broadcast TLB invalidations. We don't always set it
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* on processors that support it due to other constraints with the
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* use of such invalidations
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*/
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#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
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/* Enable use of tlbilx invalidate instructions.
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*/
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#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
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/* This indicates that the processor cannot handle multiple outstanding
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* broadcast tlbivax or tlbsync. This makes the code use a spinlock
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* around such invalidate forms.
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*/
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#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
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/* This indicates that the processor doesn't handle way selection
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* properly and needs SW to track and update the LRU state. This
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* is specific to an errata on e300c2/c3/c4 class parts
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*/
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#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
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/* Enable use of TLB reservation. Processor should support tlbsrx.
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* instruction and MAS0[WQ].
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*/
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#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
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/* Use paired MAS registers (MAS7||MAS3, etc.)
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*/
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#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
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/* Doesn't support the B bit (1T segment) in SLBIE
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*/
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#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
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/* Support 16M large pages
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*/
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#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
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/* Supports TLBIEL variant
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*/
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#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
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/* Supports tlbies w/o locking
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*/
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#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
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/* Large pages can be marked CI
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*/
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#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
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/* 1T segments available
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*/
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#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
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/* MMU feature bit sets for various CPUs */
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#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
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MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
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#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
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#define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
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#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
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#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
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#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
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#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
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#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
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#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE
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#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
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#ifndef __ASSEMBLY__
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#include <linux/bug.h>
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#include <asm/cputable.h>
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#ifdef CONFIG_PPC_FSL_BOOK3E
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#include <asm/percpu.h>
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DECLARE_PER_CPU(int, next_tlbcam_idx);
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#endif
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enum {
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MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
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MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
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MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
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MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
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MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
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MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
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MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
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MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
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MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
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MMU_FTR_KERNEL_RO |
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#ifdef CONFIG_PPC_RADIX_MMU
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MMU_FTR_TYPE_RADIX |
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#endif
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0,
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};
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static inline bool early_mmu_has_feature(unsigned long feature)
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{
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return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
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}
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#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
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#include <linux/jump_label.h>
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#define NUM_MMU_FTR_KEYS 32
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extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
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extern void mmu_feature_keys_init(void);
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static __always_inline bool mmu_has_feature(unsigned long feature)
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{
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int i;
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BUILD_BUG_ON(!__builtin_constant_p(feature));
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#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
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if (!static_key_initialized) {
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printk("Warning! mmu_has_feature() used prior to jump label init!\n");
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dump_stack();
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return early_mmu_has_feature(feature);
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}
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#endif
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if (!(MMU_FTRS_POSSIBLE & feature))
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return false;
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i = __builtin_ctzl(feature);
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return static_branch_likely(&mmu_feature_keys[i]);
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}
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static inline void mmu_clear_feature(unsigned long feature)
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{
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int i;
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i = __builtin_ctzl(feature);
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cur_cpu_spec->mmu_features &= ~feature;
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static_branch_disable(&mmu_feature_keys[i]);
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}
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#else
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static inline void mmu_feature_keys_init(void)
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{
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}
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static inline bool mmu_has_feature(unsigned long feature)
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{
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return early_mmu_has_feature(feature);
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}
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static inline void mmu_clear_feature(unsigned long feature)
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{
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cur_cpu_spec->mmu_features &= ~feature;
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}
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#endif /* CONFIG_JUMP_LABEL */
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extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
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#ifdef CONFIG_PPC64
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/* This is our real memory area size on ppc64 server, on embedded, we
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* make it match the size our of bolted TLB area
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*/
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extern u64 ppc64_rma_size;
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/* Cleanup function used by kexec */
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extern void mmu_cleanup_all(void);
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extern void radix__mmu_cleanup_all(void);
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/* Functions for creating and updating partition table on POWER9 */
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extern void mmu_partition_table_init(void);
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extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
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unsigned long dw1);
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#endif /* CONFIG_PPC64 */
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struct mm_struct;
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#ifdef CONFIG_DEBUG_VM
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extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
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#else /* CONFIG_DEBUG_VM */
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static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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}
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#endif /* !CONFIG_DEBUG_VM */
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#ifdef CONFIG_PPC_RADIX_MMU
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static inline bool radix_enabled(void)
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{
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return mmu_has_feature(MMU_FTR_TYPE_RADIX);
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}
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static inline bool early_radix_enabled(void)
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{
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return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
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}
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#else
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static inline bool radix_enabled(void)
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{
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return false;
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}
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static inline bool early_radix_enabled(void)
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{
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return false;
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}
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#endif
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#endif /* !__ASSEMBLY__ */
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/* The kernel use the constants below to index in the page sizes array.
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* The use of fixed constants for this purpose is better for performances
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* of the low level hash refill handlers.
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*
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* A non supported page size has a "shift" field set to 0
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*
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* Any new page size being implemented can get a new entry in here. Whether
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* the kernel will use it or not is a different matter though. The actual page
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* size used by hugetlbfs is not defined here and may be made variable
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*
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* Note: This array ended up being a false good idea as it's growing to the
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* point where I wonder if we should replace it with something different,
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* to think about, feedback welcome. --BenH.
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*/
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/* These are #defines as they have to be used in assembly */
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#define MMU_PAGE_4K 0
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#define MMU_PAGE_16K 1
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#define MMU_PAGE_64K 2
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#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
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#define MMU_PAGE_256K 4
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#define MMU_PAGE_512K 5
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#define MMU_PAGE_1M 6
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#define MMU_PAGE_2M 7
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#define MMU_PAGE_4M 8
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#define MMU_PAGE_8M 9
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#define MMU_PAGE_16M 10
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#define MMU_PAGE_64M 11
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#define MMU_PAGE_256M 12
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#define MMU_PAGE_1G 13
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#define MMU_PAGE_16G 14
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#define MMU_PAGE_64G 15
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/* N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 */
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#define MMU_PAGE_COUNT 16
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#ifdef CONFIG_PPC_BOOK3S_64
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#include <asm/book3s/64/mmu.h>
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#else /* CONFIG_PPC_BOOK3S_64 */
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#ifndef __ASSEMBLY__
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/* MMU initialization */
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extern void early_init_mmu(void);
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extern void early_init_mmu_secondary(void);
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extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size);
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static inline void mmu_early_init_devtree(void) { }
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#endif /* __ASSEMBLY__ */
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#endif
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#if defined(CONFIG_PPC_STD_MMU_32)
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/* 32-bit classic hash table MMU */
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#include <asm/book3s/32/mmu-hash.h>
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#elif defined(CONFIG_40x)
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/* 40x-style software loaded TLB */
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# include <asm/mmu-40x.h>
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#elif defined(CONFIG_44x)
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/* 44x-style software loaded TLB */
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# include <asm/mmu-44x.h>
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#elif defined(CONFIG_PPC_BOOK3E_MMU)
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/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
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# include <asm/mmu-book3e.h>
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#elif defined (CONFIG_PPC_8xx)
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/* Motorola/Freescale 8xx software loaded TLB */
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# include <asm/mmu-8xx.h>
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_MMU_H_ */
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