245 lines
5.3 KiB
Plaintext
245 lines
5.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Pinctrl dts file for HiSilicon HiKey970 development board
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*/
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#include <dt-bindings/pinctrl/hisi.h>
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/ {
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soc {
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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pmx0: pinmux@e896c000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xe896c000 0x0 0x72c>;
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#pinctrl-cells = <1>;
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#gpio-range-cells = <0x3>;
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pinctrl-single,register-width = <0x20>;
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pinctrl-single,function-mask = <0x7>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 82 0>;
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uart0_pmx_func: uart0_pmx_func {
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pinctrl-single,pins = <
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0x054 MUX_M2 /* UART0_RXD */
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0x058 MUX_M2 /* UART0_TXD */
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>;
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};
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uart2_pmx_func: uart2_pmx_func {
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pinctrl-single,pins = <
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0x700 MUX_M2 /* UART2_CTS_N */
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0x704 MUX_M2 /* UART2_RTS_N */
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0x708 MUX_M2 /* UART2_RXD */
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0x70c MUX_M2 /* UART2_TXD */
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>;
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};
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uart3_pmx_func: uart3_pmx_func {
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pinctrl-single,pins = <
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0x064 MUX_M1 /* UART3_CTS_N */
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0x068 MUX_M1 /* UART3_RTS_N */
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0x06c MUX_M1 /* UART3_RXD */
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0x070 MUX_M1 /* UART3_TXD */
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>;
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};
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uart4_pmx_func: uart4_pmx_func {
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pinctrl-single,pins = <
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0x074 MUX_M1 /* UART4_CTS_N */
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0x078 MUX_M1 /* UART4_RTS_N */
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0x07c MUX_M1 /* UART4_RXD */
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0x080 MUX_M1 /* UART4_TXD */
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>;
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};
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uart6_pmx_func: uart6_pmx_func {
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pinctrl-single,pins = <
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0x05c MUX_M1 /* UART6_RXD */
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0x060 MUX_M1 /* UART6_TXD */
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>;
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};
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};
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pmx2: pinmux@e896c800 {
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compatible = "pinconf-single";
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reg = <0x0 0xe896c800 0x0 0x72c>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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uart0_cfg_func: uart0_cfg_func {
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pinctrl-single,pins = <
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0x058 0x0 /* UART0_RXD */
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0x05c 0x0 /* UART0_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart2_cfg_func: uart2_cfg_func {
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pinctrl-single,pins = <
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0x700 0x0 /* UART2_CTS_N */
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0x704 0x0 /* UART2_RTS_N */
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0x708 0x0 /* UART2_RXD */
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0x70c 0x0 /* UART2_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart3_cfg_func: uart3_cfg_func {
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pinctrl-single,pins = <
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0x068 0x0 /* UART3_CTS_N */
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0x06c 0x0 /* UART3_RTS_N */
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0x070 0x0 /* UART3_RXD */
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0x074 0x0 /* UART3_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart4_cfg_func: uart4_cfg_func {
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pinctrl-single,pins = <
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0x078 0x0 /* UART4_CTS_N */
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0x07c 0x0 /* UART4_RTS_N */
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0x080 0x0 /* UART4_RXD */
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0x084 0x0 /* UART4_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart6_cfg_func: uart6_cfg_func {
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pinctrl-single,pins = <
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0x060 0x0 /* UART6_RXD */
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0x064 0x0 /* UART6_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_02MA DRIVE6_MASK
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>;
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};
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};
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pmx5: pinmux@fc182000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xfc182000 0x0 0x028>;
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#gpio-range-cells = <3>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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pinctrl-single,function-mask = <0x7>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 10 0>;
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};
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pmx6: pinmux@fc182800 {
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compatible = "pinconf-single";
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reg = <0x0 0xfc182800 0x0 0x028>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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};
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pmx7: pinmux@ff37e000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xff37e000 0x0 0x030>;
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#gpio-range-cells = <3>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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pinctrl-single,function-mask = <7>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 12 0>;
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};
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pmx8: pinmux@ff37e800 {
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compatible = "pinconf-single";
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reg = <0x0 0xff37e800 0x0 0x030>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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};
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pmx1: pinmux@fff11000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xfff11000 0x0 0x73c>;
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#gpio-range-cells = <0x3>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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pinctrl-single,function-mask = <0x7>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 46 0>;
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};
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pmx16: pinmux@fff11800 {
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compatible = "pinconf-single";
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reg = <0x0 0xfff11800 0x0 0x73c>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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};
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};
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};
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