162 lines
4.1 KiB
C
162 lines
4.1 KiB
C
/*
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* Copyright (c) 2002 Stephen Rothwell, IBM Coproration
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* Extracted from ptrace.c and ptrace32.c
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file README.legal in the main directory of
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* this archive for more details.
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*/
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#ifndef _PPC64_PTRACE_COMMON_H
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#define _PPC64_PTRACE_COMMON_H
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#include <asm/system.h>
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/*
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* Set of msr bits that gdb can change on behalf of a process.
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*/
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#define MSR_DEBUGCHANGE (MSR_FE0 | MSR_SE | MSR_BE | MSR_FE1)
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/*
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* Get contents of register REGNO in task TASK.
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*/
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static inline unsigned long get_reg(struct task_struct *task, int regno)
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{
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unsigned long tmp = 0;
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/*
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* Put the correct FP bits in, they might be wrong as a result
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* of our lazy FP restore.
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*/
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if (regno == PT_MSR) {
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tmp = ((unsigned long *)task->thread.regs)[PT_MSR];
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tmp |= task->thread.fpexc_mode;
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} else if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
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tmp = ((unsigned long *)task->thread.regs)[regno];
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}
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return tmp;
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}
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/*
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* Write contents of register REGNO in task TASK.
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*/
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static inline int put_reg(struct task_struct *task, int regno,
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unsigned long data)
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{
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if (regno < PT_SOFTE) {
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if (regno == PT_MSR)
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data = (data & MSR_DEBUGCHANGE)
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| (task->thread.regs->msr & ~MSR_DEBUGCHANGE);
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((unsigned long *)task->thread.regs)[regno] = data;
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return 0;
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}
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return -EIO;
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}
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static inline void set_single_step(struct task_struct *task)
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{
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struct pt_regs *regs = task->thread.regs;
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if (regs != NULL)
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regs->msr |= MSR_SE;
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set_tsk_thread_flag(task, TIF_SINGLESTEP);
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}
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static inline void clear_single_step(struct task_struct *task)
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{
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struct pt_regs *regs = task->thread.regs;
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if (regs != NULL)
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regs->msr &= ~MSR_SE;
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clear_tsk_thread_flag(task, TIF_SINGLESTEP);
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}
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#ifdef CONFIG_ALTIVEC
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/*
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* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
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* The transfer totals 34 quadword. Quadwords 0-31 contain the
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* corresponding vector registers. Quadword 32 contains the vscr as the
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* last word (offset 12) within that quadword. Quadword 33 contains the
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* vrsave as the first word (offset 0) within the quadword.
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*
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* This definition of the VMX state is compatible with the current PPC32
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* ptrace interface. This allows signal handling and ptrace to use the
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* same structures. This also simplifies the implementation of a bi-arch
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* (combined (32- and 64-bit) gdb.
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*/
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/*
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* Get contents of AltiVec register state in task TASK
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*/
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static inline int get_vrregs(unsigned long __user *data,
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struct task_struct *task)
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{
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unsigned long regsize;
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/* copy AltiVec registers VR[0] .. VR[31] */
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regsize = 32 * sizeof(vector128);
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if (copy_to_user(data, task->thread.vr, regsize))
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return -EFAULT;
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data += (regsize / sizeof(unsigned long));
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/* copy VSCR */
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regsize = 1 * sizeof(vector128);
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if (copy_to_user(data, &task->thread.vscr, regsize))
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return -EFAULT;
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data += (regsize / sizeof(unsigned long));
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/* copy VRSAVE */
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if (put_user(task->thread.vrsave, (u32 __user *)data))
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return -EFAULT;
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return 0;
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}
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/*
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* Write contents of AltiVec register state into task TASK.
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*/
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static inline int set_vrregs(struct task_struct *task,
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unsigned long __user *data)
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{
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unsigned long regsize;
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/* copy AltiVec registers VR[0] .. VR[31] */
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regsize = 32 * sizeof(vector128);
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if (copy_from_user(task->thread.vr, data, regsize))
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return -EFAULT;
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data += (regsize / sizeof(unsigned long));
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/* copy VSCR */
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regsize = 1 * sizeof(vector128);
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if (copy_from_user(&task->thread.vscr, data, regsize))
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return -EFAULT;
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data += (regsize / sizeof(unsigned long));
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/* copy VRSAVE */
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if (get_user(task->thread.vrsave, (u32 __user *)data))
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return -EFAULT;
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return 0;
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}
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#endif
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static inline int ptrace_set_debugreg(struct task_struct *task,
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unsigned long addr, unsigned long data)
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{
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/* We only support one DABR and no IABRS at the moment */
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if (addr > 0)
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return -EINVAL;
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/* The bottom 3 bits are flags */
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if ((data & ~0x7UL) >= TASK_SIZE)
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return -EIO;
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/* Ensure translation is on */
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if (data && !(data & DABR_TRANSLATION))
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return -EIO;
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task->thread.dabr = data;
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return 0;
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}
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#endif /* _PPC64_PTRACE_COMMON_H */
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