594 lines
14 KiB
C
594 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Amlogic MESON SoCs
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Yue Wang <yue.wang@amlogic.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
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/* External local bus interface registers */
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#define PLR_OFFSET 0x700
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#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
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#define FAST_LINK_MODE BIT(7)
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#define LINK_CAPABLE_MASK GENMASK(21, 16)
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#define LINK_CAPABLE_X1 BIT(16)
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#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
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#define NUM_OF_LANES_MASK GENMASK(12, 8)
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#define NUM_OF_LANES_X1 BIT(8)
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#define DIRECT_SPEED_CHANGE BIT(17)
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#define TYPE1_HDR_OFFSET 0x0
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#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
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#define PCI_IO_EN BIT(0)
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#define PCI_MEM_SPACE_EN BIT(1)
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#define PCI_BUS_MASTER_EN BIT(2)
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#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
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#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
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#define PCIE_CAP_OFFSET 0x70
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#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
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#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
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#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
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#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
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#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
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/* PCIe specific config registers */
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#define PCIE_CFG0 0x0
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#define APP_LTSSM_ENABLE BIT(7)
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#define PCIE_CFG_STATUS12 0x30
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#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
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#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
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#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
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#define PCIE_CFG_STATUS17 0x44
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#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
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#define WAIT_LINKUP_TIMEOUT 4000
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#define PORT_CLK_RATE 100000000UL
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#define MAX_PAYLOAD_SIZE 256
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#define MAX_READ_REQ_SIZE 256
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#define MESON_PCIE_PHY_POWERUP 0x1c
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#define PCIE_RESET_DELAY 500
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#define PCIE_SHARED_RESET 1
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#define PCIE_NORMAL_RESET 0
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enum pcie_data_rate {
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PCIE_GEN1,
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PCIE_GEN2,
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PCIE_GEN3,
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PCIE_GEN4
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};
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struct meson_pcie_mem_res {
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void __iomem *elbi_base;
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void __iomem *cfg_base;
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void __iomem *phy_base;
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};
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struct meson_pcie_clk_res {
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struct clk *clk;
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struct clk *mipi_gate;
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struct clk *port_clk;
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struct clk *general_clk;
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};
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struct meson_pcie_rc_reset {
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struct reset_control *phy;
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struct reset_control *port;
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struct reset_control *apb;
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};
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struct meson_pcie {
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struct dw_pcie pci;
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struct meson_pcie_mem_res mem_res;
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struct meson_pcie_clk_res clk_res;
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struct meson_pcie_rc_reset mrst;
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struct gpio_desc *reset_gpio;
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};
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static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
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const char *id,
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u32 reset_type)
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{
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struct device *dev = mp->pci.dev;
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struct reset_control *reset;
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if (reset_type == PCIE_SHARED_RESET)
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reset = devm_reset_control_get_shared(dev, id);
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else
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reset = devm_reset_control_get(dev, id);
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return reset;
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}
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static int meson_pcie_get_resets(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
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if (IS_ERR(mrst->phy))
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return PTR_ERR(mrst->phy);
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reset_control_deassert(mrst->phy);
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mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
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if (IS_ERR(mrst->port))
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return PTR_ERR(mrst->port);
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reset_control_deassert(mrst->port);
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mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
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if (IS_ERR(mrst->apb))
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return PTR_ERR(mrst->apb);
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reset_control_deassert(mrst->apb);
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return 0;
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}
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static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
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struct meson_pcie *mp,
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const char *id)
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{
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struct device *dev = mp->pci.dev;
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
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return devm_ioremap_resource(dev, res);
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}
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static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
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struct meson_pcie *mp,
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const char *id)
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{
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struct device *dev = mp->pci.dev;
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
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if (!res) {
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dev_err(dev, "No REG resource %s\n", id);
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return ERR_PTR(-ENXIO);
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}
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return devm_ioremap(dev, res->start, resource_size(res));
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}
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static int meson_pcie_get_mems(struct platform_device *pdev,
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struct meson_pcie *mp)
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{
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mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi");
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if (IS_ERR(mp->mem_res.elbi_base))
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return PTR_ERR(mp->mem_res.elbi_base);
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mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg");
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if (IS_ERR(mp->mem_res.cfg_base))
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return PTR_ERR(mp->mem_res.cfg_base);
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/* Meson SoC has two PCI controllers use same phy register*/
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mp->mem_res.phy_base = meson_pcie_get_mem_shared(pdev, mp, "phy");
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if (IS_ERR(mp->mem_res.phy_base))
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return PTR_ERR(mp->mem_res.phy_base);
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return 0;
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}
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static void meson_pcie_power_on(struct meson_pcie *mp)
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{
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writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
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}
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static void meson_pcie_reset(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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reset_control_assert(mrst->phy);
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udelay(PCIE_RESET_DELAY);
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reset_control_deassert(mrst->phy);
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udelay(PCIE_RESET_DELAY);
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reset_control_assert(mrst->port);
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reset_control_assert(mrst->apb);
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udelay(PCIE_RESET_DELAY);
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reset_control_deassert(mrst->port);
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reset_control_deassert(mrst->apb);
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udelay(PCIE_RESET_DELAY);
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}
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static inline struct clk *meson_pcie_probe_clock(struct device *dev,
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const char *id, u64 rate)
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{
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struct clk *clk;
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int ret;
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clk = devm_clk_get(dev, id);
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if (IS_ERR(clk))
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return clk;
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if (rate) {
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ret = clk_set_rate(clk, rate);
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if (ret) {
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dev_err(dev, "set clk rate failed, ret = %d\n", ret);
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return ERR_PTR(ret);
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}
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "couldn't enable clk\n");
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return ERR_PTR(ret);
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}
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devm_add_action_or_reset(dev,
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(void (*) (void *))clk_disable_unprepare,
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clk);
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return clk;
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}
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static int meson_pcie_probe_clocks(struct meson_pcie *mp)
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{
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struct device *dev = mp->pci.dev;
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struct meson_pcie_clk_res *res = &mp->clk_res;
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res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
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if (IS_ERR(res->port_clk))
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return PTR_ERR(res->port_clk);
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res->mipi_gate = meson_pcie_probe_clock(dev, "pcie_mipi_en", 0);
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if (IS_ERR(res->mipi_gate))
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return PTR_ERR(res->mipi_gate);
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res->general_clk = meson_pcie_probe_clock(dev, "pcie_general", 0);
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if (IS_ERR(res->general_clk))
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return PTR_ERR(res->general_clk);
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res->clk = meson_pcie_probe_clock(dev, "pcie", 0);
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if (IS_ERR(res->clk))
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return PTR_ERR(res->clk);
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return 0;
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}
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static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg)
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{
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writel(val, mp->mem_res.elbi_base + reg);
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}
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static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg)
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{
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return readl(mp->mem_res.elbi_base + reg);
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}
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static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
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{
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return readl(mp->mem_res.cfg_base + reg);
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}
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static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
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{
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writel(val, mp->mem_res.cfg_base + reg);
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}
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static void meson_pcie_assert_reset(struct meson_pcie *mp)
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{
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gpiod_set_value_cansleep(mp->reset_gpio, 0);
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udelay(500);
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gpiod_set_value_cansleep(mp->reset_gpio, 1);
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}
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static void meson_pcie_init_dw(struct meson_pcie *mp)
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{
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u32 val;
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val = meson_cfg_readl(mp, PCIE_CFG0);
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val |= APP_LTSSM_ENABLE;
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meson_cfg_writel(mp, val, PCIE_CFG0);
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val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
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val &= ~LINK_CAPABLE_MASK;
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meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
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val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
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val |= LINK_CAPABLE_X1 | FAST_LINK_MODE;
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meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
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val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
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val &= ~NUM_OF_LANES_MASK;
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meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
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val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
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val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
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meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
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meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
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meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
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}
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static int meson_size_to_payload(struct meson_pcie *mp, int size)
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{
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struct device *dev = mp->pci.dev;
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/*
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* dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
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* So if input size is not 2^order alignment or less than 2^7 or bigger
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* than 2^12, just set to default size 2^(1+7).
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*/
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if (!is_power_of_2(size) || size < 128 || size > 4096) {
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dev_warn(dev, "payload size %d, set to default 256\n", size);
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return 1;
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}
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return fls(size) - 8;
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}
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static void meson_set_max_payload(struct meson_pcie *mp, int size)
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{
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u32 val;
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int max_payload_size = meson_size_to_payload(mp, size);
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val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
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val &= ~PCIE_CAP_MAX_PAYLOAD_MASK;
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meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
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val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
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val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
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meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
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}
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static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
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{
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u32 val;
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int max_rd_req_size = meson_size_to_payload(mp, size);
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val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
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val &= ~PCIE_CAP_MAX_READ_REQ_MASK;
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meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
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val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
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val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
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meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
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}
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static inline void meson_enable_memory_space(struct meson_pcie *mp)
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{
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/* Set the RC Bus Master, Memory Space and I/O Space enables */
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meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
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PCIE_STATUS_COMMAND);
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}
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static int meson_pcie_establish_link(struct meson_pcie *mp)
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{
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struct dw_pcie *pci = &mp->pci;
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struct pcie_port *pp = &pci->pp;
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meson_pcie_init_dw(mp);
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meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
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meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
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dw_pcie_setup_rc(pp);
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meson_enable_memory_space(mp);
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meson_pcie_assert_reset(mp);
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return dw_pcie_wait_for_link(pci);
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}
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static void meson_pcie_enable_interrupts(struct meson_pcie *mp)
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{
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(&mp->pci.pp);
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}
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static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret;
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ret = dw_pcie_read(pci->dbi_base + where, size, val);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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/*
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* There is a bug in the MESON AXG PCIe controller whereby software
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* cannot program the PCI_CLASS_DEVICE register, so we must fabricate
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* the return value in the config accessors.
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*/
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if (where == PCI_CLASS_REVISION && size == 4)
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*val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
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else if (where == PCI_CLASS_DEVICE && size == 2)
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*val = PCI_CLASS_BRIDGE_PCI;
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else if (where == PCI_CLASS_DEVICE && size == 1)
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*val = PCI_CLASS_BRIDGE_PCI & 0xff;
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else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
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*val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
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return PCIBIOS_SUCCESSFUL;
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}
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static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where,
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int size, u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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return dw_pcie_write(pci->dbi_base + where, size, val);
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}
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static int meson_pcie_link_up(struct dw_pcie *pci)
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{
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struct meson_pcie *mp = to_meson_pcie(pci);
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struct device *dev = pci->dev;
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u32 speed_okay = 0;
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u32 cnt = 0;
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u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
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do {
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state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
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state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
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smlh_up = IS_SMLH_LINK_UP(state12);
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rdlh_up = IS_RDLH_LINK_UP(state12);
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ltssm_up = IS_LTSSM_UP(state12);
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if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
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speed_okay = 1;
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if (smlh_up)
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dev_dbg(dev, "smlh_link_up is on\n");
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if (rdlh_up)
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dev_dbg(dev, "rdlh_link_up is on\n");
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if (ltssm_up)
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dev_dbg(dev, "ltssm_up is on\n");
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if (speed_okay)
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dev_dbg(dev, "speed_okay\n");
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if (smlh_up && rdlh_up && ltssm_up && speed_okay)
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return 1;
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cnt++;
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udelay(10);
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} while (cnt < WAIT_LINKUP_TIMEOUT);
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dev_err(dev, "error: wait linkup timeout\n");
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return 0;
|
|
}
|
|
|
|
static int meson_pcie_host_init(struct pcie_port *pp)
|
|
{
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
struct meson_pcie *mp = to_meson_pcie(pci);
|
|
int ret;
|
|
|
|
ret = meson_pcie_establish_link(mp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
meson_pcie_enable_interrupts(mp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dw_pcie_host_ops meson_pcie_host_ops = {
|
|
.rd_own_conf = meson_pcie_rd_own_conf,
|
|
.wr_own_conf = meson_pcie_wr_own_conf,
|
|
.host_init = meson_pcie_host_init,
|
|
};
|
|
|
|
static int meson_add_pcie_port(struct meson_pcie *mp,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct dw_pcie *pci = &mp->pci;
|
|
struct pcie_port *pp = &pci->pp;
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
pp->msi_irq = platform_get_irq(pdev, 0);
|
|
if (pp->msi_irq < 0) {
|
|
dev_err(dev, "failed to get MSI IRQ\n");
|
|
return pp->msi_irq;
|
|
}
|
|
}
|
|
|
|
pp->ops = &meson_pcie_host_ops;
|
|
pci->dbi_base = mp->mem_res.elbi_base;
|
|
|
|
ret = dw_pcie_host_init(pp);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
|
.link_up = meson_pcie_link_up,
|
|
};
|
|
|
|
static int meson_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct dw_pcie *pci;
|
|
struct meson_pcie *mp;
|
|
int ret;
|
|
|
|
mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
|
|
if (!mp)
|
|
return -ENOMEM;
|
|
|
|
pci = &mp->pci;
|
|
pci->dev = dev;
|
|
pci->ops = &dw_pcie_ops;
|
|
|
|
mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
|
|
if (IS_ERR(mp->reset_gpio)) {
|
|
dev_err(dev, "get reset gpio failed\n");
|
|
return PTR_ERR(mp->reset_gpio);
|
|
}
|
|
|
|
ret = meson_pcie_get_resets(mp);
|
|
if (ret) {
|
|
dev_err(dev, "get reset resource failed, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = meson_pcie_get_mems(pdev, mp);
|
|
if (ret) {
|
|
dev_err(dev, "get memory resource failed, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
meson_pcie_power_on(mp);
|
|
meson_pcie_reset(mp);
|
|
|
|
ret = meson_pcie_probe_clocks(mp);
|
|
if (ret) {
|
|
dev_err(dev, "init clock resources failed, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, mp);
|
|
|
|
ret = meson_add_pcie_port(mp, pdev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Add PCIe port failed, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id meson_pcie_of_match[] = {
|
|
{
|
|
.compatible = "amlogic,axg-pcie",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver meson_pcie_driver = {
|
|
.probe = meson_pcie_probe,
|
|
.driver = {
|
|
.name = "meson-pcie",
|
|
.of_match_table = meson_pcie_of_match,
|
|
},
|
|
};
|
|
|
|
builtin_platform_driver(meson_pcie_driver);
|