589 lines
14 KiB
ArmAsm
589 lines
14 KiB
ArmAsm
/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <linux/errno.h>
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#include <asm/entry.h>
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#include <asm/asm-offsets.h>
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#include <asm/registers.h>
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#include <asm/unistd.h>
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#include <asm/percpu.h>
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#include <asm/signal.h>
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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.macro disable_irq
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msrclr r0, MSR_IE
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.endm
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.macro enable_irq
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msrset r0, MSR_IE
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.endm
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.macro clear_bip
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msrclr r0, MSR_BIP
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.endm
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#else
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.macro disable_irq
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mfs r11, rmsr
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andi r11, r11, ~MSR_IE
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mts rmsr, r11
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.endm
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.macro enable_irq
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mfs r11, rmsr
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ori r11, r11, MSR_IE
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mts rmsr, r11
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.endm
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.macro clear_bip
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mfs r11, rmsr
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andi r11, r11, ~MSR_BIP
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mts rmsr, r11
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.endm
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#endif
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ENTRY(_interrupt)
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swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
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swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
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lwi r11, r0, PER_CPU(KM) /* load mode indicator */
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beqid r11, 1f
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nop
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brid 2f /* jump over */
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addik r1, r1, (-PT_SIZE) /* room for pt_regs (delay slot) */
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1: /* switch to kernel stack */
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lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
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lwi r1, r1, TS_THREAD_INFO /* get the thread info */
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/* calculate kernel stack pointer */
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addik r1, r1, THREAD_SIZE - PT_SIZE
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2:
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swi r11, r1, PT_MODE /* store the mode */
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lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
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swi r2, r1, PT_R2
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swi r3, r1, PT_R3
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swi r4, r1, PT_R4
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swi r5, r1, PT_R5
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swi r6, r1, PT_R6
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swi r7, r1, PT_R7
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swi r8, r1, PT_R8
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swi r9, r1, PT_R9
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swi r10, r1, PT_R10
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swi r11, r1, PT_R11
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swi r12, r1, PT_R12
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swi r13, r1, PT_R13
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swi r14, r1, PT_R14
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swi r14, r1, PT_PC
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swi r15, r1, PT_R15
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swi r16, r1, PT_R16
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swi r17, r1, PT_R17
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swi r18, r1, PT_R18
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swi r19, r1, PT_R19
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swi r20, r1, PT_R20
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swi r21, r1, PT_R21
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swi r22, r1, PT_R22
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swi r23, r1, PT_R23
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swi r24, r1, PT_R24
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swi r25, r1, PT_R25
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swi r26, r1, PT_R26
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swi r27, r1, PT_R27
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swi r28, r1, PT_R28
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swi r29, r1, PT_R29
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swi r30, r1, PT_R30
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swi r31, r1, PT_R31
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/* special purpose registers */
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mfs r11, rmsr
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swi r11, r1, PT_MSR
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mfs r11, rear
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swi r11, r1, PT_EAR
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mfs r11, resr
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swi r11, r1, PT_ESR
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mfs r11, rfsr
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swi r11, r1, PT_FSR
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/* reload original stack pointer and save it */
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lwi r11, r0, PER_CPU(ENTRY_SP)
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swi r11, r1, PT_R1
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/* update mode indicator we are in kernel mode */
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addik r11, r0, 1
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swi r11, r0, PER_CPU(KM)
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/* restore r31 */
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lwi r31, r0, PER_CPU(CURRENT_SAVE)
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/* prepare the link register, the argument and jump */
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la r15, r0, ret_from_intr - 8
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addk r6, r0, r15
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braid do_IRQ
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add r5, r0, r1
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ret_from_intr:
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lwi r11, r1, PT_MODE
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bneid r11, 3f
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lwi r6, r31, TS_THREAD_INFO /* get thread info */
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lwi r19, r6, TI_FLAGS /* get flags in thread info */
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/* do an extra work if any bits are set */
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andi r11, r19, _TIF_NEED_RESCHED
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beqi r11, 1f
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bralid r15, schedule
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nop
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1: andi r11, r19, _TIF_SIGPENDING
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beqid r11, no_intr_reshed
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addk r5, r1, r0
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addk r7, r0, r0
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bralid r15, do_signal
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addk r6, r0, r0
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no_intr_reshed:
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/* save mode indicator */
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lwi r11, r1, PT_MODE
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3:
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swi r11, r0, PER_CPU(KM)
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/* save r31 */
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swi r31, r0, PER_CPU(CURRENT_SAVE)
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restore_context:
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/* special purpose registers */
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lwi r11, r1, PT_FSR
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mts rfsr, r11
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lwi r11, r1, PT_ESR
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mts resr, r11
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lwi r11, r1, PT_EAR
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mts rear, r11
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lwi r11, r1, PT_MSR
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mts rmsr, r11
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lwi r31, r1, PT_R31
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lwi r30, r1, PT_R30
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lwi r29, r1, PT_R29
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lwi r28, r1, PT_R28
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lwi r27, r1, PT_R27
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lwi r26, r1, PT_R26
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lwi r25, r1, PT_R25
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lwi r24, r1, PT_R24
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lwi r23, r1, PT_R23
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lwi r22, r1, PT_R22
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lwi r21, r1, PT_R21
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lwi r20, r1, PT_R20
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lwi r19, r1, PT_R19
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lwi r18, r1, PT_R18
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lwi r17, r1, PT_R17
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lwi r16, r1, PT_R16
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lwi r15, r1, PT_R15
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lwi r14, r1, PT_PC
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lwi r13, r1, PT_R13
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lwi r12, r1, PT_R12
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lwi r11, r1, PT_R11
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lwi r10, r1, PT_R10
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lwi r9, r1, PT_R9
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lwi r8, r1, PT_R8
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lwi r7, r1, PT_R7
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lwi r6, r1, PT_R6
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lwi r5, r1, PT_R5
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lwi r4, r1, PT_R4
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lwi r3, r1, PT_R3
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lwi r2, r1, PT_R2
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lwi r1, r1, PT_R1
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rtid r14, 0
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nop
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ENTRY(_reset)
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brai 0;
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ENTRY(_user_exception)
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swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
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swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
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lwi r11, r0, PER_CPU(KM) /* load mode indicator */
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beqid r11, 1f /* Already in kernel mode? */
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nop
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brid 2f /* jump over */
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addik r1, r1, (-PT_SIZE) /* Room for pt_regs (delay slot) */
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1: /* Switch to kernel stack */
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lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
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lwi r1, r1, TS_THREAD_INFO /* get the thread info */
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/* calculate kernel stack pointer */
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addik r1, r1, THREAD_SIZE - PT_SIZE
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swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
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lwi r11, r0, PER_CPU(KM) /* load mode indicator */
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2:
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swi r11, r1, PT_MODE /* store the mode */
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lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
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/* save them on stack */
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swi r2, r1, PT_R2
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swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
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swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
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swi r5, r1, PT_R5
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swi r6, r1, PT_R6
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swi r7, r1, PT_R7
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swi r8, r1, PT_R8
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swi r9, r1, PT_R9
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swi r10, r1, PT_R10
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swi r11, r1, PT_R11
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/* r12: _always_ in clobber list; see unistd.h */
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swi r12, r1, PT_R12
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swi r13, r1, PT_R13
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/* r14: _always_ in clobber list; see unistd.h */
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swi r14, r1, PT_R14
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/* but we want to return to the next inst. */
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addik r14, r14, 0x4
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swi r14, r1, PT_PC /* increment by 4 and store in pc */
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swi r15, r1, PT_R15
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swi r16, r1, PT_R16
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swi r17, r1, PT_R17
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swi r18, r1, PT_R18
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swi r19, r1, PT_R19
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swi r20, r1, PT_R20
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swi r21, r1, PT_R21
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swi r22, r1, PT_R22
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swi r23, r1, PT_R23
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swi r24, r1, PT_R24
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swi r25, r1, PT_R25
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swi r26, r1, PT_R26
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swi r27, r1, PT_R27
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swi r28, r1, PT_R28
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swi r29, r1, PT_R29
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swi r30, r1, PT_R30
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swi r31, r1, PT_R31
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disable_irq
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nop /* make sure IE bit is in effect */
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clear_bip /* once IE is in effect it is safe to clear BIP */
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nop
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/* special purpose registers */
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mfs r11, rmsr
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swi r11, r1, PT_MSR
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mfs r11, rear
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swi r11, r1, PT_EAR
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mfs r11, resr
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swi r11, r1, PT_ESR
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mfs r11, rfsr
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swi r11, r1, PT_FSR
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/* reload original stack pointer and save it */
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lwi r11, r0, PER_CPU(ENTRY_SP)
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swi r11, r1, PT_R1
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/* update mode indicator we are in kernel mode */
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addik r11, r0, 1
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swi r11, r0, PER_CPU(KM)
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/* restore r31 */
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lwi r31, r0, PER_CPU(CURRENT_SAVE)
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/* re-enable interrupts now we are in kernel mode */
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enable_irq
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/* See if the system call number is valid. */
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addi r11, r12, -__NR_syscalls
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bgei r11, 1f /* return to user if not valid */
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/* Figure out which function to use for this system call. */
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/* Note Microblaze barrel shift is optional, so don't rely on it */
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add r12, r12, r12 /* convert num -> ptr */
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add r12, r12, r12
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lwi r12, r12, sys_call_table /* Get function pointer */
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la r15, r0, ret_to_user-8 /* set return address */
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bra r12 /* Make the system call. */
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bri 0 /* won't reach here */
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1:
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brid ret_to_user /* jump to syscall epilogue */
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addi r3, r0, -ENOSYS /* set errno in delay slot */
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/*
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* Debug traps are like a system call, but entered via brki r14, 0x60
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* All we need to do is send the SIGTRAP signal to current, ptrace and do_signal
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* will handle the rest
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*/
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ENTRY(_debug_exception)
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swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
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lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
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lwi r1, r1, TS_THREAD_INFO /* get the thread info */
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addik r1, r1, THREAD_SIZE - PT_SIZE /* get the kernel stack */
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swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
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lwi r11, r0, PER_CPU(KM) /* load mode indicator */
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//save_context:
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swi r11, r1, PT_MODE /* store the mode */
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lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
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/* save them on stack */
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swi r2, r1, PT_R2
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swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
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swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
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swi r5, r1, PT_R5
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swi r6, r1, PT_R6
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swi r7, r1, PT_R7
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swi r8, r1, PT_R8
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swi r9, r1, PT_R9
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swi r10, r1, PT_R10
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swi r11, r1, PT_R11
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/* r12: _always_ in clobber list; see unistd.h */
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swi r12, r1, PT_R12
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swi r13, r1, PT_R13
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/* r14: _always_ in clobber list; see unistd.h */
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swi r14, r1, PT_R14
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swi r14, r1, PT_PC /* Will return to interrupted instruction */
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swi r15, r1, PT_R15
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swi r16, r1, PT_R16
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swi r17, r1, PT_R17
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swi r18, r1, PT_R18
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swi r19, r1, PT_R19
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swi r20, r1, PT_R20
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swi r21, r1, PT_R21
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swi r22, r1, PT_R22
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swi r23, r1, PT_R23
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swi r24, r1, PT_R24
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swi r25, r1, PT_R25
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swi r26, r1, PT_R26
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swi r27, r1, PT_R27
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swi r28, r1, PT_R28
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swi r29, r1, PT_R29
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swi r30, r1, PT_R30
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swi r31, r1, PT_R31
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disable_irq
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nop /* make sure IE bit is in effect */
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clear_bip /* once IE is in effect it is safe to clear BIP */
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nop
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/* special purpose registers */
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mfs r11, rmsr
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swi r11, r1, PT_MSR
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mfs r11, rear
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swi r11, r1, PT_EAR
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mfs r11, resr
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swi r11, r1, PT_ESR
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mfs r11, rfsr
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swi r11, r1, PT_FSR
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/* reload original stack pointer and save it */
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lwi r11, r0, PER_CPU(ENTRY_SP)
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swi r11, r1, PT_R1
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/* update mode indicator we are in kernel mode */
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addik r11, r0, 1
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swi r11, r0, PER_CPU(KM)
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/* restore r31 */
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lwi r31, r0, PER_CPU(CURRENT_SAVE)
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/* re-enable interrupts now we are in kernel mode */
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enable_irq
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addi r5, r0, SIGTRAP /* sending the trap signal */
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add r6, r0, r31 /* to current */
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bralid r15, send_sig
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add r7, r0, r0 /* 3rd param zero */
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/* Restore r3/r4 to work around how ret_to_user works */
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lwi r3, r1, PT_R3
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lwi r4, r1, PT_R4
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bri ret_to_user
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ENTRY(_break)
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bri 0
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/* struct task_struct *_switch_to(struct thread_info *prev,
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struct thread_info *next); */
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ENTRY(_switch_to)
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/* prepare return value */
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addk r3, r0, r31
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/* save registers in cpu_context */
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/* use r11 and r12, volatile registers, as temp register */
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addik r11, r5, TI_CPU_CONTEXT
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swi r1, r11, CC_R1
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swi r2, r11, CC_R2
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/* skip volatile registers.
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* they are saved on stack when we jumped to _switch_to() */
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/* dedicated registers */
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swi r13, r11, CC_R13
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swi r14, r11, CC_R14
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swi r15, r11, CC_R15
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swi r16, r11, CC_R16
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swi r17, r11, CC_R17
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swi r18, r11, CC_R18
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/* save non-volatile registers */
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swi r19, r11, CC_R19
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swi r20, r11, CC_R20
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swi r21, r11, CC_R21
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swi r22, r11, CC_R22
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swi r23, r11, CC_R23
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swi r24, r11, CC_R24
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swi r25, r11, CC_R25
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swi r26, r11, CC_R26
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swi r27, r11, CC_R27
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swi r28, r11, CC_R28
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swi r29, r11, CC_R29
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swi r30, r11, CC_R30
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/* special purpose registers */
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mfs r12, rmsr
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swi r12, r11, CC_MSR
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mfs r12, rear
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swi r12, r11, CC_EAR
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mfs r12, resr
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swi r12, r11, CC_ESR
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mfs r12, rfsr
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swi r12, r11, CC_FSR
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/* update r31, the current */
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lwi r31, r6, TI_TASK
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swi r31, r0, PER_CPU(CURRENT_SAVE)
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/* get new process' cpu context and restore */
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addik r11, r6, TI_CPU_CONTEXT
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/* special purpose registers */
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lwi r12, r11, CC_FSR
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mts rfsr, r12
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lwi r12, r11, CC_ESR
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mts resr, r12
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lwi r12, r11, CC_EAR
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mts rear, r12
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lwi r12, r11, CC_MSR
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mts rmsr, r12
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/* non-volatile registers */
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lwi r30, r11, CC_R30
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lwi r29, r11, CC_R29
|
|
lwi r28, r11, CC_R28
|
|
lwi r27, r11, CC_R27
|
|
lwi r26, r11, CC_R26
|
|
lwi r25, r11, CC_R25
|
|
lwi r24, r11, CC_R24
|
|
lwi r23, r11, CC_R23
|
|
lwi r22, r11, CC_R22
|
|
lwi r21, r11, CC_R21
|
|
lwi r20, r11, CC_R20
|
|
lwi r19, r11, CC_R19
|
|
/* dedicated registers */
|
|
lwi r18, r11, CC_R18
|
|
lwi r17, r11, CC_R17
|
|
lwi r16, r11, CC_R16
|
|
lwi r15, r11, CC_R15
|
|
lwi r14, r11, CC_R14
|
|
lwi r13, r11, CC_R13
|
|
/* skip volatile registers */
|
|
lwi r2, r11, CC_R2
|
|
lwi r1, r11, CC_R1
|
|
|
|
rtsd r15, 8
|
|
nop
|
|
|
|
ENTRY(ret_from_fork)
|
|
addk r5, r0, r3
|
|
addk r6, r0, r1
|
|
brlid r15, schedule_tail
|
|
nop
|
|
swi r31, r1, PT_R31 /* save r31 in user context. */
|
|
/* will soon be restored to r31 in ret_to_user */
|
|
addk r3, r0, r0
|
|
brid ret_to_user
|
|
nop
|
|
|
|
work_pending:
|
|
andi r11, r19, _TIF_NEED_RESCHED
|
|
beqi r11, 1f
|
|
bralid r15, schedule
|
|
nop
|
|
1: andi r11, r19, _TIF_SIGPENDING
|
|
beqi r11, no_work_pending
|
|
addk r5, r1, r0
|
|
addik r7, r0, 1
|
|
bralid r15, do_signal
|
|
addk r6, r0, r0
|
|
bri no_work_pending
|
|
|
|
ENTRY(ret_to_user)
|
|
disable_irq
|
|
|
|
swi r4, r1, PT_R4 /* return val */
|
|
swi r3, r1, PT_R3 /* return val */
|
|
|
|
lwi r6, r31, TS_THREAD_INFO /* get thread info */
|
|
lwi r19, r6, TI_FLAGS /* get flags in thread info */
|
|
bnei r19, work_pending /* do an extra work if any bits are set */
|
|
no_work_pending:
|
|
disable_irq
|
|
|
|
/* save r31 */
|
|
swi r31, r0, PER_CPU(CURRENT_SAVE)
|
|
/* save mode indicator */
|
|
lwi r18, r1, PT_MODE
|
|
swi r18, r0, PER_CPU(KM)
|
|
//restore_context:
|
|
/* special purpose registers */
|
|
lwi r18, r1, PT_FSR
|
|
mts rfsr, r18
|
|
lwi r18, r1, PT_ESR
|
|
mts resr, r18
|
|
lwi r18, r1, PT_EAR
|
|
mts rear, r18
|
|
lwi r18, r1, PT_MSR
|
|
mts rmsr, r18
|
|
|
|
lwi r31, r1, PT_R31
|
|
lwi r30, r1, PT_R30
|
|
lwi r29, r1, PT_R29
|
|
lwi r28, r1, PT_R28
|
|
lwi r27, r1, PT_R27
|
|
lwi r26, r1, PT_R26
|
|
lwi r25, r1, PT_R25
|
|
lwi r24, r1, PT_R24
|
|
lwi r23, r1, PT_R23
|
|
lwi r22, r1, PT_R22
|
|
lwi r21, r1, PT_R21
|
|
lwi r20, r1, PT_R20
|
|
lwi r19, r1, PT_R19
|
|
lwi r18, r1, PT_R18
|
|
lwi r17, r1, PT_R17
|
|
lwi r16, r1, PT_R16
|
|
lwi r15, r1, PT_R15
|
|
lwi r14, r1, PT_PC
|
|
lwi r13, r1, PT_R13
|
|
lwi r12, r1, PT_R12
|
|
lwi r11, r1, PT_R11
|
|
lwi r10, r1, PT_R10
|
|
lwi r9, r1, PT_R9
|
|
lwi r8, r1, PT_R8
|
|
lwi r7, r1, PT_R7
|
|
lwi r6, r1, PT_R6
|
|
lwi r5, r1, PT_R5
|
|
lwi r4, r1, PT_R4 /* return val */
|
|
lwi r3, r1, PT_R3 /* return val */
|
|
lwi r2, r1, PT_R2
|
|
lwi r1, r1, PT_R1
|
|
|
|
rtid r14, 0
|
|
nop
|
|
|
|
sys_vfork:
|
|
brid microblaze_vfork
|
|
addk r5, r1, r0
|
|
|
|
sys_clone:
|
|
brid microblaze_clone
|
|
addk r7, r1, r0
|
|
|
|
sys_execve:
|
|
brid microblaze_execve
|
|
addk r8, r1, r0
|
|
|
|
sys_rt_sigreturn_wrapper:
|
|
brid sys_rt_sigreturn
|
|
addk r5, r1, r0
|
|
|
|
sys_rt_sigsuspend_wrapper:
|
|
brid sys_rt_sigsuspend
|
|
addk r7, r1, r0
|
|
|
|
/* Interrupt vector table */
|
|
.section .init.ivt, "ax"
|
|
.org 0x0
|
|
brai _reset
|
|
brai _user_exception
|
|
brai _interrupt
|
|
brai _break
|
|
brai _hw_exception_handler
|
|
.org 0x60
|
|
brai _debug_exception
|
|
|
|
.section .rodata,"a"
|
|
#include "syscall_table.S"
|
|
|
|
syscall_table_size=(.-sys_call_table)
|