528 lines
14 KiB
C
528 lines
14 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv40.h"
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#include "regs.h"
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#include <core/client.h>
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#include <core/handle.h>
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#include <subdev/fb.h>
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#include <subdev/timer.h>
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#include <engine/fifo.h>
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struct nv40_gr_priv {
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struct nvkm_gr base;
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u32 size;
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};
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struct nv40_gr_chan {
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struct nvkm_gr_chan base;
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};
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static u64
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nv40_gr_units(struct nvkm_gr *gr)
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{
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struct nv40_gr_priv *priv = (void *)gr;
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return nv_rd32(priv, 0x1540);
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}
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/*******************************************************************************
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* Graphics object classes
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******************************************************************************/
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static int
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nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nvkm_gpuobj *obj;
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int ret;
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ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
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20, 16, 0, &obj);
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*pobject = nv_object(obj);
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if (ret)
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return ret;
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nv_wo32(obj, 0x00, nv_mclass(obj));
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nv_wo32(obj, 0x04, 0x00000000);
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nv_wo32(obj, 0x08, 0x00000000);
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#ifdef __BIG_ENDIAN
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nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
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#endif
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nv_wo32(obj, 0x0c, 0x00000000);
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nv_wo32(obj, 0x10, 0x00000000);
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return 0;
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}
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static struct nvkm_ofuncs
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nv40_gr_ofuncs = {
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.ctor = nv40_gr_object_ctor,
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.dtor = _nvkm_gpuobj_dtor,
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.init = _nvkm_gpuobj_init,
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.fini = _nvkm_gpuobj_fini,
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.rd32 = _nvkm_gpuobj_rd32,
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.wr32 = _nvkm_gpuobj_wr32,
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};
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static struct nvkm_oclass
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nv40_gr_sclass[] = {
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{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
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{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
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{ 0x0030, &nv40_gr_ofuncs, NULL }, /* null */
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{ 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */
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{ 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */
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{ 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */
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{ 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */
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{ 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */
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{ 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */
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{ 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */
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{ 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */
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{ 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */
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{ 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */
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{ 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */
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{ 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */
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{ 0x4097, &nv40_gr_ofuncs, NULL }, /* curie */
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{},
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};
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static struct nvkm_oclass
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nv44_gr_sclass[] = {
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{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
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{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
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{ 0x0030, &nv40_gr_ofuncs, NULL }, /* null */
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{ 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */
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{ 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */
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{ 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */
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{ 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */
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{ 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */
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{ 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */
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{ 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */
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{ 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */
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{ 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */
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{ 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */
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{ 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */
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{ 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */
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{ 0x4497, &nv40_gr_ofuncs, NULL }, /* curie */
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{},
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};
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/*******************************************************************************
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* PGRAPH context
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******************************************************************************/
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static int
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nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv40_gr_priv *priv = (void *)engine;
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struct nv40_gr_chan *chan;
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int ret;
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ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
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16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
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nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
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return 0;
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}
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static int
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nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
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{
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struct nv40_gr_priv *priv = (void *)object->engine;
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struct nv40_gr_chan *chan = (void *)object;
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u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
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int ret = 0;
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nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
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if (nv_rd32(priv, 0x40032c) == inst) {
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if (suspend) {
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nv_wr32(priv, 0x400720, 0x00000000);
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nv_wr32(priv, 0x400784, inst);
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nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
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nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
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if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
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u32 insn = nv_rd32(priv, 0x400308);
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nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
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ret = -EBUSY;
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}
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}
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nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
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}
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if (nv_rd32(priv, 0x400330) == inst)
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nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
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nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
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return ret;
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}
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static struct nvkm_oclass
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nv40_gr_cclass = {
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.handle = NV_ENGCTX(GR, 0x40),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv40_gr_context_ctor,
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.dtor = _nvkm_gr_context_dtor,
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.init = _nvkm_gr_context_init,
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.fini = nv40_gr_context_fini,
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.rd32 = _nvkm_gr_context_rd32,
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.wr32 = _nvkm_gr_context_wr32,
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},
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};
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static void
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nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
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{
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struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
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struct nvkm_fifo *pfifo = nvkm_fifo(engine);
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struct nv40_gr_priv *priv = (void *)engine;
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unsigned long flags;
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pfifo->pause(pfifo, &flags);
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nv04_gr_idle(priv);
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switch (nv_device(priv)->chipset) {
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x45:
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case 0x4e:
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nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
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nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
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switch (nv_device(priv)->chipset) {
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case 0x40:
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case 0x45:
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nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
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nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
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break;
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case 0x41:
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case 0x42:
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case 0x43:
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nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
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nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
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break;
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default:
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break;
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}
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break;
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case 0x44:
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case 0x4a:
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nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
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break;
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case 0x46:
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case 0x4c:
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case 0x47:
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case 0x49:
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case 0x4b:
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case 0x63:
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case 0x67:
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case 0x68:
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nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
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nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
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nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
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nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
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switch (nv_device(priv)->chipset) {
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case 0x47:
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case 0x49:
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case 0x4b:
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nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
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nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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pfifo->start(pfifo, &flags);
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}
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static void
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nv40_gr_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
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struct nvkm_engine *engine = nv_engine(subdev);
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struct nvkm_object *engctx;
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struct nvkm_handle *handle = NULL;
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struct nv40_gr_priv *priv = (void *)subdev;
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u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
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u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
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u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
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u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
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u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
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u32 subc = (addr & 0x00070000) >> 16;
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u32 mthd = (addr & 0x00001ffc);
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u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
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u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
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u32 show = stat;
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int chid;
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engctx = nvkm_engctx_get(engine, inst);
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chid = pfifo->chid(pfifo, engctx);
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if (stat & NV_PGRAPH_INTR_ERROR) {
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if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
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handle = nvkm_handle_get_class(engctx, class);
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if (handle && !nv_call(handle->object, mthd, data))
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show &= ~NV_PGRAPH_INTR_ERROR;
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nvkm_handle_put(handle);
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}
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if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
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nv_mask(priv, 0x402000, 0, 0);
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}
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}
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nv_wr32(priv, NV03_PGRAPH_INTR, stat);
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nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
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if (show) {
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nv_error(priv, "%s", "");
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nvkm_bitfield_print(nv10_gr_intr_name, show);
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pr_cont(" nsource:");
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nvkm_bitfield_print(nv04_gr_nsource, nsource);
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pr_cont(" nstatus:");
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nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
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pr_cont("\n");
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nv_error(priv,
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"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
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chid, inst << 4, nvkm_client_name(engctx), subc,
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class, mthd, data);
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}
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nvkm_engctx_put(engctx);
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}
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static int
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nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv40_gr_priv *priv;
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int ret;
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ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00001000;
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nv_subdev(priv)->intr = nv40_gr_intr;
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nv_engine(priv)->cclass = &nv40_gr_cclass;
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if (nv44_gr_class(priv))
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nv_engine(priv)->sclass = nv44_gr_sclass;
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else
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nv_engine(priv)->sclass = nv40_gr_sclass;
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nv_engine(priv)->tile_prog = nv40_gr_tile_prog;
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priv->base.units = nv40_gr_units;
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return 0;
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}
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static int
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nv40_gr_init(struct nvkm_object *object)
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{
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struct nvkm_engine *engine = nv_engine(object);
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struct nvkm_fb *fb = nvkm_fb(object);
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struct nv40_gr_priv *priv = (void *)engine;
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int ret, i, j;
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u32 vramsz;
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ret = nvkm_gr_init(&priv->base);
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if (ret)
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return ret;
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/* generate and upload context program */
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ret = nv40_grctx_init(nv_device(priv), &priv->size);
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if (ret)
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return ret;
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/* No context present currently */
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nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
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nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
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nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
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nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
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nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
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nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
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nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
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nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
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nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
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nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
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j = nv_rd32(priv, 0x1540) & 0xff;
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if (j) {
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for (i = 0; !(j & 1); j >>= 1, i++)
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;
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nv_wr32(priv, 0x405000, i);
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}
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if (nv_device(priv)->chipset == 0x40) {
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nv_wr32(priv, 0x4009b0, 0x83280fff);
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nv_wr32(priv, 0x4009b4, 0x000000a0);
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} else {
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nv_wr32(priv, 0x400820, 0x83280eff);
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nv_wr32(priv, 0x400824, 0x000000a0);
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}
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switch (nv_device(priv)->chipset) {
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case 0x40:
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case 0x45:
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nv_wr32(priv, 0x4009b8, 0x0078e366);
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nv_wr32(priv, 0x4009bc, 0x0000014c);
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break;
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case 0x41:
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case 0x42: /* pciid also 0x00Cx */
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/* case 0x0120: XXX (pciid) */
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nv_wr32(priv, 0x400828, 0x007596ff);
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nv_wr32(priv, 0x40082c, 0x00000108);
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break;
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case 0x43:
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nv_wr32(priv, 0x400828, 0x0072cb77);
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nv_wr32(priv, 0x40082c, 0x00000108);
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break;
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case 0x44:
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case 0x46: /* G72 */
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case 0x4a:
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case 0x4c: /* G7x-based C51 */
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case 0x4e:
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nv_wr32(priv, 0x400860, 0);
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nv_wr32(priv, 0x400864, 0);
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break;
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
|
|
nv_wr32(priv, 0x400828, 0x07830610);
|
|
nv_wr32(priv, 0x40082c, 0x0000016A);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
nv_wr32(priv, 0x400b38, 0x2ffff800);
|
|
nv_wr32(priv, 0x400b3c, 0x00006000);
|
|
|
|
/* Tiling related stuff. */
|
|
switch (nv_device(priv)->chipset) {
|
|
case 0x44:
|
|
case 0x4a:
|
|
nv_wr32(priv, 0x400bc4, 0x1003d888);
|
|
nv_wr32(priv, 0x400bbc, 0xb7a7b500);
|
|
break;
|
|
case 0x46:
|
|
nv_wr32(priv, 0x400bc4, 0x0000e024);
|
|
nv_wr32(priv, 0x400bbc, 0xb7a7b520);
|
|
break;
|
|
case 0x4c:
|
|
case 0x4e:
|
|
case 0x67:
|
|
nv_wr32(priv, 0x400bc4, 0x1003d888);
|
|
nv_wr32(priv, 0x400bbc, 0xb7a7b540);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Turn all the tiling regions off. */
|
|
for (i = 0; i < fb->tile.regions; i++)
|
|
engine->tile_prog(engine, i);
|
|
|
|
/* begin RAM config */
|
|
vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
|
|
switch (nv_device(priv)->chipset) {
|
|
case 0x40:
|
|
nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
|
|
nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
|
|
nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
|
|
nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
|
|
nv_wr32(priv, 0x400820, 0);
|
|
nv_wr32(priv, 0x400824, 0);
|
|
nv_wr32(priv, 0x400864, vramsz);
|
|
nv_wr32(priv, 0x400868, vramsz);
|
|
break;
|
|
default:
|
|
switch (nv_device(priv)->chipset) {
|
|
case 0x41:
|
|
case 0x42:
|
|
case 0x43:
|
|
case 0x45:
|
|
case 0x4e:
|
|
case 0x44:
|
|
case 0x4a:
|
|
nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
|
|
nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
|
|
break;
|
|
default:
|
|
nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
|
|
nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
|
|
break;
|
|
}
|
|
nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
|
|
nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
|
|
nv_wr32(priv, 0x400840, 0);
|
|
nv_wr32(priv, 0x400844, 0);
|
|
nv_wr32(priv, 0x4008A0, vramsz);
|
|
nv_wr32(priv, 0x4008A4, vramsz);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct nvkm_oclass
|
|
nv40_gr_oclass = {
|
|
.handle = NV_ENGINE(GR, 0x40),
|
|
.ofuncs = &(struct nvkm_ofuncs) {
|
|
.ctor = nv40_gr_ctor,
|
|
.dtor = _nvkm_gr_dtor,
|
|
.init = nv40_gr_init,
|
|
.fini = _nvkm_gr_fini,
|
|
},
|
|
};
|