126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
#include "nv20.h"
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#include "regs.h"
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#include <engine/fifo.h>
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/*******************************************************************************
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* PGRAPH context
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******************************************************************************/
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static int
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nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv20_gr_chan *chan;
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int ret, i;
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ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
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16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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chan->chid = nvkm_fifo_chan(parent)->chid;
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nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
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nv_wo32(chan, 0x033c, 0xffff0000);
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nv_wo32(chan, 0x03a0, 0x0fff0000);
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nv_wo32(chan, 0x03a4, 0x0fff0000);
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nv_wo32(chan, 0x047c, 0x00000101);
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nv_wo32(chan, 0x0490, 0x00000111);
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nv_wo32(chan, 0x04a8, 0x44400000);
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for (i = 0x04d4; i <= 0x04e0; i += 4)
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nv_wo32(chan, i, 0x00030303);
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for (i = 0x04f4; i <= 0x0500; i += 4)
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nv_wo32(chan, i, 0x00080000);
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for (i = 0x050c; i <= 0x0518; i += 4)
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nv_wo32(chan, i, 0x01012000);
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for (i = 0x051c; i <= 0x0528; i += 4)
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nv_wo32(chan, i, 0x000105b8);
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for (i = 0x052c; i <= 0x0538; i += 4)
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nv_wo32(chan, i, 0x00080008);
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for (i = 0x055c; i <= 0x0598; i += 4)
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nv_wo32(chan, i, 0x07ff0000);
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nv_wo32(chan, 0x05a4, 0x4b7fffff);
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nv_wo32(chan, 0x05fc, 0x00000001);
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nv_wo32(chan, 0x0604, 0x00004000);
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nv_wo32(chan, 0x0610, 0x00000001);
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nv_wo32(chan, 0x0618, 0x00040000);
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nv_wo32(chan, 0x061c, 0x00010000);
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for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
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nv_wo32(chan, (i + 0), 0x10700ff9);
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nv_wo32(chan, (i + 4), 0x0436086c);
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nv_wo32(chan, (i + 8), 0x000c001b);
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}
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nv_wo32(chan, 0x269c, 0x3f800000);
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nv_wo32(chan, 0x26b0, 0x3f800000);
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nv_wo32(chan, 0x26dc, 0x40000000);
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nv_wo32(chan, 0x26e0, 0x3f800000);
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nv_wo32(chan, 0x26e4, 0x3f000000);
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nv_wo32(chan, 0x26ec, 0x40000000);
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nv_wo32(chan, 0x26f0, 0x3f800000);
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nv_wo32(chan, 0x26f8, 0xbf800000);
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nv_wo32(chan, 0x2700, 0xbf800000);
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nv_wo32(chan, 0x3024, 0x000fe000);
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nv_wo32(chan, 0x30a0, 0x000003f8);
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nv_wo32(chan, 0x33fc, 0x002fe000);
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for (i = 0x341c; i <= 0x3438; i += 4)
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nv_wo32(chan, i, 0x001c527c);
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return 0;
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}
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static struct nvkm_oclass
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nv2a_gr_cclass = {
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.handle = NV_ENGCTX(GR, 0x2a),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv2a_gr_context_ctor,
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.dtor = _nvkm_gr_context_dtor,
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.init = nv20_gr_context_init,
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.fini = nv20_gr_context_fini,
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.rd32 = _nvkm_gr_context_rd32,
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.wr32 = _nvkm_gr_context_wr32,
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},
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};
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static int
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nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv20_gr_priv *priv;
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int ret;
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ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00001000;
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nv_subdev(priv)->intr = nv20_gr_intr;
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nv_engine(priv)->cclass = &nv2a_gr_cclass;
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nv_engine(priv)->sclass = nv25_gr_sclass;
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nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
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return 0;
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}
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struct nvkm_oclass
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nv2a_gr_oclass = {
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.handle = NV_ENGINE(GR, 0x2a),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv2a_gr_ctor,
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.dtor = nv20_gr_dtor,
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.init = nv20_gr_init,
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.fini = _nvkm_gr_fini,
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},
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};
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