159 lines
4.8 KiB
C
159 lines
4.8 KiB
C
#include "nv20.h"
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#include "regs.h"
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#include <engine/fifo.h>
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/*******************************************************************************
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* Graphics object classes
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******************************************************************************/
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struct nvkm_oclass
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nv25_gr_sclass[] = {
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{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
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{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
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{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
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{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
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{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
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{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
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{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
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{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
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{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
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{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
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{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
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{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
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{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
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{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
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{ 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */
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{},
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};
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/*******************************************************************************
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* PGRAPH context
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******************************************************************************/
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static int
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nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv20_gr_chan *chan;
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int ret, i;
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ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724,
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16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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chan->chid = nvkm_fifo_chan(parent)->chid;
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nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
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nv_wo32(chan, 0x035c, 0xffff0000);
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nv_wo32(chan, 0x03c0, 0x0fff0000);
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nv_wo32(chan, 0x03c4, 0x0fff0000);
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nv_wo32(chan, 0x049c, 0x00000101);
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nv_wo32(chan, 0x04b0, 0x00000111);
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nv_wo32(chan, 0x04c8, 0x00000080);
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nv_wo32(chan, 0x04cc, 0xffff0000);
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nv_wo32(chan, 0x04d0, 0x00000001);
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nv_wo32(chan, 0x04e4, 0x44400000);
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nv_wo32(chan, 0x04fc, 0x4b800000);
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for (i = 0x0510; i <= 0x051c; i += 4)
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nv_wo32(chan, i, 0x00030303);
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for (i = 0x0530; i <= 0x053c; i += 4)
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nv_wo32(chan, i, 0x00080000);
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for (i = 0x0548; i <= 0x0554; i += 4)
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nv_wo32(chan, i, 0x01012000);
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for (i = 0x0558; i <= 0x0564; i += 4)
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nv_wo32(chan, i, 0x000105b8);
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for (i = 0x0568; i <= 0x0574; i += 4)
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nv_wo32(chan, i, 0x00080008);
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for (i = 0x0598; i <= 0x05d4; i += 4)
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nv_wo32(chan, i, 0x07ff0000);
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nv_wo32(chan, 0x05e0, 0x4b7fffff);
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nv_wo32(chan, 0x0620, 0x00000080);
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nv_wo32(chan, 0x0624, 0x30201000);
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nv_wo32(chan, 0x0628, 0x70605040);
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nv_wo32(chan, 0x062c, 0xb0a09080);
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nv_wo32(chan, 0x0630, 0xf0e0d0c0);
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nv_wo32(chan, 0x0664, 0x00000001);
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nv_wo32(chan, 0x066c, 0x00004000);
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nv_wo32(chan, 0x0678, 0x00000001);
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nv_wo32(chan, 0x0680, 0x00040000);
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nv_wo32(chan, 0x0684, 0x00010000);
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for (i = 0x1b04; i <= 0x2374; i += 16) {
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nv_wo32(chan, (i + 0), 0x10700ff9);
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nv_wo32(chan, (i + 4), 0x0436086c);
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nv_wo32(chan, (i + 8), 0x000c001b);
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}
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nv_wo32(chan, 0x2704, 0x3f800000);
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nv_wo32(chan, 0x2718, 0x3f800000);
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nv_wo32(chan, 0x2744, 0x40000000);
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nv_wo32(chan, 0x2748, 0x3f800000);
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nv_wo32(chan, 0x274c, 0x3f000000);
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nv_wo32(chan, 0x2754, 0x40000000);
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nv_wo32(chan, 0x2758, 0x3f800000);
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nv_wo32(chan, 0x2760, 0xbf800000);
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nv_wo32(chan, 0x2768, 0xbf800000);
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nv_wo32(chan, 0x308c, 0x000fe000);
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nv_wo32(chan, 0x3108, 0x000003f8);
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nv_wo32(chan, 0x3468, 0x002fe000);
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for (i = 0x3484; i <= 0x34a0; i += 4)
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nv_wo32(chan, i, 0x001c527c);
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return 0;
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}
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static struct nvkm_oclass
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nv25_gr_cclass = {
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.handle = NV_ENGCTX(GR, 0x25),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv25_gr_context_ctor,
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.dtor = _nvkm_gr_context_dtor,
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.init = nv20_gr_context_init,
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.fini = nv20_gr_context_fini,
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.rd32 = _nvkm_gr_context_rd32,
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.wr32 = _nvkm_gr_context_wr32,
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},
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};
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static int
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nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv20_gr_priv *priv;
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int ret;
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ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00001000;
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nv_subdev(priv)->intr = nv20_gr_intr;
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nv_engine(priv)->cclass = &nv25_gr_cclass;
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nv_engine(priv)->sclass = nv25_gr_sclass;
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nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
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return 0;
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}
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struct nvkm_oclass
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nv25_gr_oclass = {
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.handle = NV_ENGINE(GR, 0x25),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv25_gr_ctor,
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.dtor = nv20_gr_dtor,
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.init = nv20_gr_init,
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.fini = _nvkm_gr_fini,
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},
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};
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