132 lines
5.6 KiB
C
132 lines
5.6 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include <subdev/bios.h>
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#include <subdev/bus.h>
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#include <subdev/gpio.h>
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#include <subdev/i2c.h>
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#include <subdev/clk.h>
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#include <subdev/therm.h>
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#include <subdev/devinit.h>
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#include <subdev/mc.h>
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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#include <subdev/instmem.h>
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#include <subdev/mmu.h>
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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#include <engine/sw.h>
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#include <engine/gr.h>
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#include <engine/disp.h>
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int
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nv20_identify(struct nvkm_device *device)
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{
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switch (device->chipset) {
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case 0x20:
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device->cname = "NV20";
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
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break;
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case 0x25:
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device->cname = "NV25";
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
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break;
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case 0x28:
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device->cname = "NV28";
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
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break;
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case 0x2a:
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device->cname = "NV2A";
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
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break;
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default:
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nv_fatal(device, "unknown Kelvin chipset\n");
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return -EINVAL;
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}
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return 0;
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}
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