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OpenCloudOS-Kernel/drivers/clk
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Bartlomiej Zolnierkiewicz d8d919879e clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support 
This flag is needed to fix the issue with wrong dividers being setup
by Common Clock Framework when using the new Exynos cpu clock support.

The issue happens because clk_core_set_rate_nolock()  calls
clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
a chance to run.  In case of Exynos cpu clock support pre/post clock
notifiers are registered for mout_apll clock which is a parent of armclk
cpu clock and dividers are modified in both pre and post clock notifier.
This results in wrong dividers values being later programmed by
clk_change_rate(top).  To workaround the problem CLK_RECALC_NEW_RATES
flag is added and it is set for mout_apll clock later so the correct
divider values are re-calculated after both pre and post clock notifiers
had run.

For example when using "performance" governor on Exynos4210 Origen board
the cpufreq-dt driver requests to change the frequency from 1000MHz to
1200MHz and after the change state of the relevant clocks is following:

Without use of CLK_GET_RATE_NOCACHE flag:

 fout_apll rate: 1200000000
         fout_apll_div_2 rate: 600000000
                 mout_clkout_cpu rate: 600000000
                         div_clkout_cpu rate: 600000000
                                 clkout_cpu rate: 600000000
         mout_apll rate: 1200000000
                 armclk rate: 1200000000
                 mout_hpm rate: 1200000000
                         div_copy rate: 300000000
                                 div_hpm rate: 300000000
                 mout_core rate: 1200000000
                         div_core rate: 1200000000
                                 div_core2 rate: 1200000000
                                         arm_clk_div_2 rate: 600000000
                                         div_corem0 rate: 300000000
                                         div_corem1 rate: 150000000
                                         div_periph rate: 300000000
                         div_atb rate: 300000000
                                 div_pclk_dbg rate: 150000000
                 sclk_apll rate: 1200000000
                         sclk_apll_div_2 rate: 600000000

With use of CLK_GET_RATE_NOCACHE flag:

 fout_apll rate: 1200000000
         fout_apll_div_2 rate: 600000000
                 mout_clkout_cpu rate: 600000000
                         div_clkout_cpu rate: 600000000
                                 clkout_cpu rate: 600000000
         mout_apll rate: 1200000000
                 armclk rate: 1200000000
                 mout_hpm rate: 1200000000
                         div_copy rate: 200000000
                                 div_hpm rate: 200000000
                 mout_core rate: 1200000000
                         div_core rate: 1200000000
                                 div_core2 rate: 1200000000
                                         arm_clk_div_2 rate: 600000000
                                         div_corem0 rate: 300000000
                                         div_corem1 rate: 150000000
                                         div_periph rate: 300000000
                         div_atb rate: 240000000
                                 div_pclk_dbg rate: 120000000
                 sclk_apll rate: 150000000
                         sclk_apll_div_2 rate: 75000000

Without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board.

This issue was probably meant to be workarounded by use of
CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
samsung: remove unused clock aliases and update clock flags" patch)
but usage of these flags is not sufficient to fix the issue observed.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
 		2015-06-20 12:17:41 -07:00
..
at91 The changes to the common clock framework for 4.0 are mostly new clock 2015-04-21 09:24:09 -07:00
bcm clk: bcm/kona: use DIV_ROUND_CLOSEST_ULL() 2015-04-17 09:03:55 -04:00
berlin clk: berlin: bg2q: remove non-exist "smemc" gate clock 2015-01-13 10:58:43 -08:00
hisilicon clk: don't use __initconst for non-const arrays 2015-04-12 17:18:27 -07:00
keystone clk: keystone: gate: fix clk_init_data initialization 2014-02-10 15:17:43 -05:00
mmp clk: Add rate constraints to clocks 2015-02-02 14:23:42 -08:00
mvebu clk: mvebu: add Marvell Armada 39x driver 2015-03-04 15:18:53 +01:00
mxs clk: don't use __initconst for non-const arrays 2015-04-12 17:18:27 -07:00
pistachio CLK: Pistachio: Register external clock gates 2015-03-31 11:59:31 +02:00
pxa clk: don't use __initconst for non-const arrays 2015-04-12 17:18:27 -07:00
qcom clk: qcom: Fix MSM8916 gfx3d_clk_src configuration 2015-04-30 18:42:55 -07:00
rockchip clk: don't use __initconst for non-const arrays 2015-04-12 17:18:27 -07:00
samsung clk: exynos5420: Restore GATE_BUS_TOP on suspend 2015-05-05 10:51:04 +02:00
shmobile ARM: shmobile: r8a7778: common clock framework CPG driver 2015-02-27 09:49:25 +09:00
sirf clk: sirf: update copyright years to 2014 2014-03-26 21:47:35 -07:00
socfpga Adds support getting the divider registers for the MAIN PLL that was once 2014-05-12 19:11:13 -07:00
spear Merge branch 'clk-fixes' into clk-next 2014-07-13 07:56:45 -07:00
st clk: constify of_device_id array 2015-04-01 10:59:27 -07:00
sunxi clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 2015-03-25 11:46:41 -07:00
tegra clk: tegra: Use the proper parent for plld_dsi 2015-04-10 16:04:22 +02:00
ti clk: don't use __initconst for non-const arrays 2015-04-12 17:18:27 -07:00
ux500 clk: ux500: Drop use of clk-private.h 2015-01-27 11:56:33 -08:00
versatile clk: versatile: test returned value 2015-04-09 08:19:31 -07:00
x86 clk: x86: drop owner assignment from platform_drivers 2014-10-20 16:20:23 +02:00
zynq clk: don't use __initconst for non-const arrays 2015-04-12 17:18:27 -07:00
Kconfig clk: Add PWM clock driver 2015-04-10 14:44:43 -07:00
Makefile The changes to the common clock framework for 4.0 are mostly new clock 2015-04-21 09:24:09 -07:00
clk-asm9260.c ARM: clk: add clk-asm9260 driver 2015-01-20 10:10:51 -08:00
clk-axi-clkgen.c clk: Remove .owner field for driver 2014-09-25 17:43:31 -07:00
clk-axm5516.c clk: drop owner assignment from platform_drivers 2014-10-20 16:20:22 +02:00
clk-bcm2835.c ARM: bcm2835: remove custom .init_time hook 2013-09-29 21:09:24 +02:00
clk-cdce706.c clk: cdce706: Constify struct regmap_config 2015-03-27 00:23:27 -07:00
clk-clps711x.c clk: Add CLPS711X clk driver 2014-07-28 23:30:46 -07:00
clk-composite.c clk: Replace explicit clk assignment with __clk_hw_set_clk 2015-02-18 09:40:11 -08:00
clk-conf.c clk: Replace of_clk_get_by_clkspec() with of_clk_get_from_provider() 2015-03-12 12:20:34 -07:00
clk-devres.c
…
clk-divider.c clk: divider: fix calculation of initial best divider when rounding to closest 2015-03-09 14:20:17 -07:00
clk-efm32gg.c clk/efm32gg: fix dt init prototype 2014-09-09 13:52:18 -07:00
clk-fixed-factor.c Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial 2013-11-15 16:47:22 -08:00
clk-fixed-rate.c clk: add accuracy support for fixed clock 2013-12-22 23:14:28 -08:00
clk-fractional-divider.c clk: fractional-divider: support for divider bypassing 2015-03-12 12:18:47 -07:00
clk-gate.c clk-gate: fix bit # check in clk_register_gate() 2015-01-20 10:09:05 -08:00
clk-gpio-gate.c clk: clk-gpio-gate: Fix active low 2015-04-10 17:45:30 -07:00
clk-highbank.c ARM: highbank: remove custom .init_time hook 2013-09-29 21:09:29 +02:00
clk-ls1x.c clk: ls1x: Update relationship among all clocks 2014-11-24 07:45:09 +01:00
clk-max-gen.c clk: Add generic driver for Maxim PMIC clocks 2014-09-09 13:55:44 -07:00
clk-max-gen.h clk: Add generic driver for Maxim PMIC clocks 2014-09-09 13:55:44 -07:00
clk-max77686.c clk: Remove .owner field for driver 2014-09-25 17:43:31 -07:00
clk-max77802.c clk: Remove .owner field for driver 2014-09-25 17:43:31 -07:00
clk-mb86s7x.c clk: Add clock driver for mb86s7x 2015-04-10 13:51:55 -07:00
clk-moxart.c clk: add MOXA ART SoCs clock driver 2014-03-18 17:13:14 -07:00
clk-mux.c clk: Add clk_unregister_{divider, gate, mux} to close memory leak 2015-01-17 13:52:41 -08:00
clk-nomadik.c clk: nomadik: fix multiplatform problem 2014-02-26 11:14:44 -08:00
clk-nspire.c clk: Add TI-Nspire clock drivers 2013-05-31 12:07:45 -07:00
clk-palmas.c clk: constify of_device_id array 2015-04-01 10:59:27 -07:00
clk-pwm.c clk: Add PWM clock driver 2015-04-10 14:44:43 -07:00
clk-qoriq.c clk: qoriq: Add support for the platform PLL 2015-02-18 09:56:43 -08:00
clk-rk808.c clk: RK808: add clkout driver for RK808 2014-10-14 02:18:18 +02:00
clk-s2mps11.c Please consider pulling the clk framework changes toward 3.19. It is 2014-12-20 16:42:36 -08:00
clk-si570.c clk: si570: Constify struct regmap_config 2015-03-27 00:22:49 -07:00
clk-si5351.c clk: si5351: Do not pass struct clk in platform_data 2015-05-08 11:22:30 -07:00
clk-si5351.h clk: si5351: remove variant from platform_data 2014-01-27 11:20:22 -08:00
clk-twl6040.c clk: Remove .owner field for driver 2014-09-25 17:43:31 -07:00
clk-u300.c clk: u300: Terminate of match table 2014-05-27 18:29:04 -07:00
clk-vt8500.c clk: vt8500: Staticize vtwm_pll_ops 2013-12-19 17:47:32 -08:00
clk-wm831x.c clk: Remove .owner field for driver 2014-09-25 17:43:31 -07:00
clk-xgene.c clk: Add APM X-Gene SoC clock driver 2013-10-07 11:22:15 -07:00
clk.c clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support 2015-06-20 12:17:41 -07:00
clk.h clk: Replace of_clk_get_by_clkspec() with of_clk_get_from_provider() 2015-03-12 12:20:34 -07:00
clkdev.c clk: Replace of_clk_get_by_clkspec() with of_clk_get_from_provider() 2015-03-12 12:20:34 -07:00