197 lines
4.5 KiB
C
197 lines
4.5 KiB
C
/* bnx2x_init.h: Broadcom Everest network driver.
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* Structures and macroes needed during the initialization.
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*
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* Copyright (c) 2007-2009 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Modified by: Vladislav Zolotarov <vladz@broadcom.com>
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*/
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#ifndef BNX2X_INIT_H
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#define BNX2X_INIT_H
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/* RAM0 size in bytes */
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#define STORM_INTMEM_SIZE_E1 0x5800
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#define STORM_INTMEM_SIZE_E1H 0x10000
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#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
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STORM_INTMEM_SIZE_E1H) / 4)
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/* Init operation types and structures */
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/* Common for both E1 and E1H */
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#define OP_RD 0x1 /* read single register */
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#define OP_WR 0x2 /* write single register */
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#define OP_IW 0x3 /* write single register using mailbox */
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#define OP_SW 0x4 /* copy a string to the device */
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#define OP_SI 0x5 /* copy a string using mailbox */
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#define OP_ZR 0x6 /* clear memory */
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#define OP_ZP 0x7 /* unzip then copy with DMAE */
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#define OP_WR_64 0x8 /* write 64 bit pattern */
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#define OP_WB 0x9 /* copy a string using DMAE */
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/* FPGA and EMUL specific operations */
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#define OP_WR_EMUL 0xa /* write single register on Emulation */
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#define OP_WR_FPGA 0xb /* write single register on FPGA */
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#define OP_WR_ASIC 0xc /* write single register on ASIC */
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/* Init stages */
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/* Never reorder stages !!! */
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#define COMMON_STAGE 0
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#define PORT0_STAGE 1
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#define PORT1_STAGE 2
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#define FUNC0_STAGE 3
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#define FUNC1_STAGE 4
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#define FUNC2_STAGE 5
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#define FUNC3_STAGE 6
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#define FUNC4_STAGE 7
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#define FUNC5_STAGE 8
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#define FUNC6_STAGE 9
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#define FUNC7_STAGE 10
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#define STAGE_IDX_MAX 11
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#define STAGE_START 0
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#define STAGE_END 1
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/* Indices of blocks */
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#define PRS_BLOCK 0
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#define SRCH_BLOCK 1
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#define TSDM_BLOCK 2
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#define TCM_BLOCK 3
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#define BRB1_BLOCK 4
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#define TSEM_BLOCK 5
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#define PXPCS_BLOCK 6
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#define EMAC0_BLOCK 7
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#define EMAC1_BLOCK 8
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#define DBU_BLOCK 9
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#define MISC_BLOCK 10
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#define DBG_BLOCK 11
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#define NIG_BLOCK 12
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#define MCP_BLOCK 13
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#define UPB_BLOCK 14
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#define CSDM_BLOCK 15
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#define USDM_BLOCK 16
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#define CCM_BLOCK 17
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#define UCM_BLOCK 18
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#define USEM_BLOCK 19
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#define CSEM_BLOCK 20
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#define XPB_BLOCK 21
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#define DQ_BLOCK 22
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#define TIMERS_BLOCK 23
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#define XSDM_BLOCK 24
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#define QM_BLOCK 25
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#define PBF_BLOCK 26
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#define XCM_BLOCK 27
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#define XSEM_BLOCK 28
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#define CDU_BLOCK 29
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#define DMAE_BLOCK 30
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#define PXP_BLOCK 31
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#define CFC_BLOCK 32
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#define HC_BLOCK 33
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#define PXP2_BLOCK 34
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#define MISC_AEU_BLOCK 35
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#define PGLUE_B_BLOCK 36
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#define IGU_BLOCK 37
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#define ATC_BLOCK 38
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#define QM_4PORT_BLOCK 39
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#define XSEM_4PORT_BLOCK 40
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/* Returns the index of start or end of a specific block stage in ops array*/
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#define BLOCK_OPS_IDX(block, stage, end) \
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(2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
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struct raw_op {
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u32 op:8;
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u32 offset:24;
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u32 raw_data;
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};
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struct op_read {
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u32 op:8;
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u32 offset:24;
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u32 pad;
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};
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struct op_write {
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u32 op:8;
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u32 offset:24;
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u32 val;
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};
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struct op_string_write {
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u32 op:8;
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u32 offset:24;
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#ifdef __LITTLE_ENDIAN
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u16 data_off;
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u16 data_len;
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#else /* __BIG_ENDIAN */
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u16 data_len;
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u16 data_off;
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#endif
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};
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struct op_zero {
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u32 op:8;
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u32 offset:24;
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u32 len;
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};
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union init_op {
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struct op_read read;
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struct op_write write;
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struct op_string_write str_wr;
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struct op_zero zero;
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struct raw_op raw;
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};
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#define INITOP_SET 0 /* set the HW directly */
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#define INITOP_CLEAR 1 /* clear the HW directly */
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#define INITOP_INIT 2 /* set the init-value array */
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/****************************************************************************
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* ILT management
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****************************************************************************/
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struct ilt_line {
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dma_addr_t page_mapping;
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void *page;
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u32 size;
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};
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struct ilt_client_info {
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u32 page_size;
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u16 start;
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u16 end;
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u16 client_num;
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u16 flags;
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#define ILT_CLIENT_SKIP_INIT 0x1
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#define ILT_CLIENT_SKIP_MEM 0x2
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};
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struct bnx2x_ilt {
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u32 start_line;
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struct ilt_line *lines;
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struct ilt_client_info clients[4];
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#define ILT_CLIENT_CDU 0
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#define ILT_CLIENT_QM 1
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#define ILT_CLIENT_SRC 2
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#define ILT_CLIENT_TM 3
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};
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/****************************************************************************
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* SRC configuration
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****************************************************************************/
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struct src_ent {
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u8 opaque[56];
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u64 next;
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};
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#endif /* BNX2X_INIT_H */
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