347 lines
8.1 KiB
C
347 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmaengine.h>
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#include <uapi/linux/idxd.h>
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#include "../dmaengine.h"
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#include "registers.h"
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#include "idxd.h"
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static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c)
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{
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struct idxd_dma_chan *idxd_chan;
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idxd_chan = container_of(c, struct idxd_dma_chan, chan);
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return idxd_chan->wq;
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}
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void idxd_dma_complete_txd(struct idxd_desc *desc,
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enum idxd_complete_type comp_type)
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{
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struct dma_async_tx_descriptor *tx;
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struct dmaengine_result res;
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int complete = 1;
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if (desc->completion->status == DSA_COMP_SUCCESS)
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res.result = DMA_TRANS_NOERROR;
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else if (desc->completion->status)
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res.result = DMA_TRANS_WRITE_FAILED;
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else if (comp_type == IDXD_COMPLETE_ABORT)
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res.result = DMA_TRANS_ABORTED;
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else
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complete = 0;
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tx = &desc->txd;
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if (complete && tx->cookie) {
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dma_cookie_complete(tx);
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dma_descriptor_unmap(tx);
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dmaengine_desc_get_callback_invoke(tx, &res);
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tx->callback = NULL;
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tx->callback_result = NULL;
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}
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}
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static void op_flag_setup(unsigned long flags, u32 *desc_flags)
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{
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*desc_flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR;
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if (flags & DMA_PREP_INTERRUPT)
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*desc_flags |= IDXD_OP_FLAG_RCI;
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}
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static inline void set_completion_address(struct idxd_desc *desc,
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u64 *compl_addr)
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{
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*compl_addr = desc->compl_dma;
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}
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static inline void idxd_prep_desc_common(struct idxd_wq *wq,
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struct dsa_hw_desc *hw, char opcode,
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u64 addr_f1, u64 addr_f2, u64 len,
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u64 compl, u32 flags)
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{
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hw->flags = flags;
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hw->opcode = opcode;
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hw->src_addr = addr_f1;
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hw->dst_addr = addr_f2;
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hw->xfer_size = len;
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hw->priv = !!(wq->type == IDXD_WQT_KERNEL);
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hw->completion_addr = compl;
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}
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static struct dma_async_tx_descriptor *
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idxd_dma_submit_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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dma_addr_t dma_src, size_t len, unsigned long flags)
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{
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struct idxd_wq *wq = to_idxd_wq(c);
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u32 desc_flags;
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struct idxd_device *idxd = wq->idxd;
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struct idxd_desc *desc;
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if (wq->state != IDXD_WQ_ENABLED)
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return NULL;
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if (len > idxd->max_xfer_bytes)
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return NULL;
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op_flag_setup(flags, &desc_flags);
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desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);
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if (IS_ERR(desc))
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return NULL;
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idxd_prep_desc_common(wq, desc->hw, DSA_OPCODE_MEMMOVE,
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dma_src, dma_dest, len, desc->compl_dma,
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desc_flags);
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desc->txd.flags = flags;
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return &desc->txd;
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}
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static int idxd_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct idxd_wq *wq = to_idxd_wq(chan);
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struct device *dev = &wq->idxd->pdev->dev;
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idxd_wq_get(wq);
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dev_dbg(dev, "%s: client_count: %d\n", __func__,
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idxd_wq_refcount(wq));
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return 0;
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}
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static void idxd_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct idxd_wq *wq = to_idxd_wq(chan);
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struct device *dev = &wq->idxd->pdev->dev;
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idxd_wq_put(wq);
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dev_dbg(dev, "%s: client_count: %d\n", __func__,
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idxd_wq_refcount(wq));
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}
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static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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return DMA_OUT_OF_ORDER;
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}
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/*
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* issue_pending() does not need to do anything since tx_submit() does the job
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* already.
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*/
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static void idxd_dma_issue_pending(struct dma_chan *dma_chan)
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{
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}
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static dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct dma_chan *c = tx->chan;
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struct idxd_wq *wq = to_idxd_wq(c);
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dma_cookie_t cookie;
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int rc;
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struct idxd_desc *desc = container_of(tx, struct idxd_desc, txd);
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cookie = dma_cookie_assign(tx);
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rc = idxd_submit_desc(wq, desc);
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if (rc < 0) {
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idxd_free_desc(wq, desc);
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return rc;
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}
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return cookie;
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}
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static void idxd_dma_release(struct dma_device *device)
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{
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struct idxd_dma_dev *idxd_dma = container_of(device, struct idxd_dma_dev, dma);
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kfree(idxd_dma);
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}
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int idxd_register_dma_device(struct idxd_device *idxd)
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{
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struct idxd_dma_dev *idxd_dma;
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struct dma_device *dma;
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struct device *dev = &idxd->pdev->dev;
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int rc;
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idxd_dma = kzalloc_node(sizeof(*idxd_dma), GFP_KERNEL, dev_to_node(dev));
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if (!idxd_dma)
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return -ENOMEM;
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dma = &idxd_dma->dma;
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INIT_LIST_HEAD(&dma->channels);
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dma->dev = dev;
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dma_cap_set(DMA_PRIVATE, dma->cap_mask);
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dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask);
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dma->device_release = idxd_dma_release;
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if (idxd->hw.opcap.bits[0] & IDXD_OPCAP_MEMMOVE) {
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dma_cap_set(DMA_MEMCPY, dma->cap_mask);
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dma->device_prep_dma_memcpy = idxd_dma_submit_memcpy;
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}
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dma->device_tx_status = idxd_dma_tx_status;
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dma->device_issue_pending = idxd_dma_issue_pending;
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dma->device_alloc_chan_resources = idxd_dma_alloc_chan_resources;
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dma->device_free_chan_resources = idxd_dma_free_chan_resources;
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rc = dma_async_device_register(dma);
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if (rc < 0) {
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kfree(idxd_dma);
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return rc;
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}
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idxd_dma->idxd = idxd;
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/*
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* This pointer is protected by the refs taken by the dma_chan. It will remain valid
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* as long as there are outstanding channels.
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*/
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idxd->idxd_dma = idxd_dma;
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return 0;
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}
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void idxd_unregister_dma_device(struct idxd_device *idxd)
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{
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dma_async_device_unregister(&idxd->idxd_dma->dma);
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}
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int idxd_register_dma_channel(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct dma_device *dma = &idxd->idxd_dma->dma;
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struct device *dev = &idxd->pdev->dev;
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struct idxd_dma_chan *idxd_chan;
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struct dma_chan *chan;
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int rc, i;
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idxd_chan = kzalloc_node(sizeof(*idxd_chan), GFP_KERNEL, dev_to_node(dev));
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if (!idxd_chan)
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return -ENOMEM;
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chan = &idxd_chan->chan;
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chan->device = dma;
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list_add_tail(&chan->device_node, &dma->channels);
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for (i = 0; i < wq->num_descs; i++) {
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struct idxd_desc *desc = wq->descs[i];
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dma_async_tx_descriptor_init(&desc->txd, chan);
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desc->txd.tx_submit = idxd_dma_tx_submit;
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}
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rc = dma_async_device_channel_register(dma, chan);
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if (rc < 0) {
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kfree(idxd_chan);
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return rc;
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}
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wq->idxd_chan = idxd_chan;
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idxd_chan->wq = wq;
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get_device(wq_confdev(wq));
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return 0;
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}
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void idxd_unregister_dma_channel(struct idxd_wq *wq)
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{
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struct idxd_dma_chan *idxd_chan = wq->idxd_chan;
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struct dma_chan *chan = &idxd_chan->chan;
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struct idxd_dma_dev *idxd_dma = wq->idxd->idxd_dma;
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dma_async_device_channel_unregister(&idxd_dma->dma, chan);
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list_del(&chan->device_node);
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kfree(wq->idxd_chan);
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wq->idxd_chan = NULL;
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put_device(wq_confdev(wq));
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}
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static int idxd_dmaengine_drv_probe(struct idxd_dev *idxd_dev)
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{
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struct device *dev = &idxd_dev->conf_dev;
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struct idxd_wq *wq = idxd_dev_to_wq(idxd_dev);
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struct idxd_device *idxd = wq->idxd;
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int rc;
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if (idxd->state != IDXD_DEV_ENABLED)
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return -ENXIO;
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mutex_lock(&wq->wq_lock);
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wq->type = IDXD_WQT_KERNEL;
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rc = __drv_enable_wq(wq);
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if (rc < 0) {
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dev_dbg(dev, "Enable wq %d failed: %d\n", wq->id, rc);
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rc = -ENXIO;
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goto err;
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}
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rc = idxd_wq_alloc_resources(wq);
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if (rc < 0) {
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idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR;
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dev_dbg(dev, "WQ resource alloc failed\n");
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goto err_res_alloc;
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}
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rc = idxd_wq_init_percpu_ref(wq);
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if (rc < 0) {
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idxd->cmd_status = IDXD_SCMD_PERCPU_ERR;
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dev_dbg(dev, "percpu_ref setup failed\n");
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goto err_ref;
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}
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rc = idxd_register_dma_channel(wq);
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if (rc < 0) {
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idxd->cmd_status = IDXD_SCMD_DMA_CHAN_ERR;
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dev_dbg(dev, "Failed to register dma channel\n");
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goto err_dma;
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}
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idxd->cmd_status = 0;
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mutex_unlock(&wq->wq_lock);
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return 0;
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err_dma:
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idxd_wq_quiesce(wq);
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err_ref:
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idxd_wq_free_resources(wq);
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err_res_alloc:
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__drv_disable_wq(wq);
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err:
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wq->type = IDXD_WQT_NONE;
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mutex_unlock(&wq->wq_lock);
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return rc;
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}
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static void idxd_dmaengine_drv_remove(struct idxd_dev *idxd_dev)
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{
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struct idxd_wq *wq = idxd_dev_to_wq(idxd_dev);
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mutex_lock(&wq->wq_lock);
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idxd_wq_quiesce(wq);
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idxd_unregister_dma_channel(wq);
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__drv_disable_wq(wq);
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idxd_wq_free_resources(wq);
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wq->type = IDXD_WQT_NONE;
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mutex_unlock(&wq->wq_lock);
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}
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static enum idxd_dev_type dev_types[] = {
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IDXD_DEV_WQ,
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IDXD_DEV_NONE,
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};
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struct idxd_device_driver idxd_dmaengine_drv = {
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.probe = idxd_dmaengine_drv_probe,
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.remove = idxd_dmaengine_drv_remove,
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.name = "dmaengine",
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.type = dev_types,
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};
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EXPORT_SYMBOL_GPL(idxd_dmaengine_drv);
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