395 lines
9.6 KiB
Plaintext
395 lines
9.6 KiB
Plaintext
/*
|
|
* Device Tree Source for UniPhier PXs2 SoC
|
|
*
|
|
* Copyright (C) 2015-2016 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "socionext,uniphier-pxs2";
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
clocks = <&sys_clk 32>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
operating-points-v2 = <&cpu_opp>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
clocks = <&sys_clk 32>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
operating-points-v2 = <&cpu_opp>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <2>;
|
|
clocks = <&sys_clk 32>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
operating-points-v2 = <&cpu_opp>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <3>;
|
|
clocks = <&sys_clk 32>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
operating-points-v2 = <&cpu_opp>;
|
|
};
|
|
};
|
|
|
|
cpu_opp: opp_table {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp@100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@150000000 {
|
|
opp-hz = /bits/ 64 <150000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@400000000 {
|
|
opp-hz = /bits/ 64 <400000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@800000000 {
|
|
opp-hz = /bits/ 64 <800000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp@1200000000 {
|
|
opp-hz = /bits/ 64 <1200000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
clocks {
|
|
refclk: ref {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
};
|
|
|
|
arm_timer_clk: arm_timer_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <50000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
interrupt-parent = <&intc>;
|
|
|
|
l2: l2-cache@500c0000 {
|
|
compatible = "socionext,uniphier-system-cache";
|
|
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
|
<0x506c0000 0x400>;
|
|
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
|
|
cache-unified;
|
|
cache-size = <(1280 * 1024)>;
|
|
cache-sets = <512>;
|
|
cache-line-size = <128>;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
serial0: serial@54006800 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006800 0x40>;
|
|
interrupts = <0 33 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart0>;
|
|
clocks = <&peri_clk 0>;
|
|
};
|
|
|
|
serial1: serial@54006900 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006900 0x40>;
|
|
interrupts = <0 35 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
clocks = <&peri_clk 1>;
|
|
};
|
|
|
|
serial2: serial@54006a00 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006a00 0x40>;
|
|
interrupts = <0 37 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
clocks = <&peri_clk 2>;
|
|
};
|
|
|
|
serial3: serial@54006b00 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006b00 0x40>;
|
|
interrupts = <0 177 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
|
clocks = <&peri_clk 3>;
|
|
};
|
|
|
|
i2c0: i2c@58780000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58780000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 41 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
clocks = <&peri_clk 4>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c1: i2c@58781000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58781000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 42 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clocks = <&peri_clk 5>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c2: i2c@58782000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58782000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 43 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
clocks = <&peri_clk 6>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c3: i2c@58783000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58783000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 44 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
clocks = <&peri_clk 7>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
/* chip-internal connection for DMD */
|
|
i2c4: i2c@58784000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58784000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 45 4>;
|
|
clocks = <&peri_clk 8>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
/* chip-internal connection for STM */
|
|
i2c5: i2c@58785000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58785000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 25 4>;
|
|
clocks = <&peri_clk 9>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
/* chip-internal connection for HDMI */
|
|
i2c6: i2c@58786000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58786000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 26 4>;
|
|
clocks = <&peri_clk 10>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
system_bus: system-bus@58c00000 {
|
|
compatible = "socionext,uniphier-system-bus";
|
|
status = "disabled";
|
|
reg = <0x58c00000 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_system_bus>;
|
|
};
|
|
|
|
smpctrl@59800000 {
|
|
compatible = "socionext,uniphier-smpctrl";
|
|
reg = <0x59801000 0x400>;
|
|
};
|
|
|
|
sdctrl@59810000 {
|
|
compatible = "socionext,uniphier-pxs2-sdctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59810000 0x800>;
|
|
|
|
sd_clk: clock {
|
|
compatible = "socionext,uniphier-pxs2-sd-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sd_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-sd-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
perictrl@59820000 {
|
|
compatible = "socionext,uniphier-pxs2-perictrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59820000 0x200>;
|
|
|
|
peri_clk: clock {
|
|
compatible = "socionext,uniphier-pxs2-peri-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
peri_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-peri-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
soc-glue@5f800000 {
|
|
compatible = "socionext,uniphier-pxs2-soc-glue",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x5f800000 0x2000>;
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "socionext,uniphier-pxs2-pinctrl";
|
|
};
|
|
};
|
|
|
|
timer@60000200 {
|
|
compatible = "arm,cortex-a9-global-timer";
|
|
reg = <0x60000200 0x20>;
|
|
interrupts = <1 11 0xf04>;
|
|
clocks = <&arm_timer_clk>;
|
|
};
|
|
|
|
timer@60000600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x60000600 0x20>;
|
|
interrupts = <1 13 0xf04>;
|
|
clocks = <&arm_timer_clk>;
|
|
};
|
|
|
|
intc: interrupt-controller@60001000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0x60001000 0x1000>,
|
|
<0x60000100 0x100>;
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
sysctrl@61840000 {
|
|
compatible = "socionext,uniphier-pxs2-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
sys_clk: clock {
|
|
compatible = "socionext,uniphier-pxs2-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sys_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "uniphier-pinctrl.dtsi"
|