141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/gt64120.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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/*
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* PCI configuration cycle AD bus definition
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*/
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/* Type 0 */
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#define PCI_CFG_TYPE0_REG_SHF 0
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#define PCI_CFG_TYPE0_FUNC_SHF 8
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/* Type 1 */
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#define PCI_CFG_TYPE1_REG_SHF 0
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#define PCI_CFG_TYPE1_FUNC_SHF 8
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#define PCI_CFG_TYPE1_DEV_SHF 11
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#define PCI_CFG_TYPE1_BUS_SHF 16
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static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
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{
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unsigned char busnum = bus->number;
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u32 intr;
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if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
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return -1; /* Because of a bug in the galileo (for slot 31). */
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/* Clear cause register bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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/* Setup address */
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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if (access_type == PCI_ACCESS_WRITE) {
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if (busnum == 0 && PCI_SLOT(devfn) == 0) {
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/*
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* The Galileo system controller is acting
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* differently than other devices.
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*/
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GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
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} else
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__GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
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} else {
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if (busnum == 0 && PCI_SLOT(devfn) == 0) {
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/*
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* The Galileo system controller is acting
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* differently than other devices.
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*/
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*data = GT_READ(GT_PCI0_CFGDATA_OFS);
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} else
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*data = __GT_READ(GT_PCI0_CFGDATA_OFS);
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}
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/* Check for master or target abort */
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intr = GT_READ(GT_INTRCAUSE_OFS);
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if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
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/* Error occurred */
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/* Clear bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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return -1;
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}
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return 0;
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}
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/*
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
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where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4)
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data = val;
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else {
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
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where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops gt64xxx_pci0_ops = {
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.read = gt64xxx_pci0_pcibios_read,
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.write = gt64xxx_pci0_pcibios_write
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};
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