Will Deacon d675d0bc47 ARM: LPAE: add ISBs around MMU enabling code ... Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2011-12-08 10:30:38 +00:00
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asm	ARM: LPAE: add ISBs around MMU enabling code	2011-12-08 10:30:38 +00:00