Samuel Holland 864a024250 riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma ... [ Upstream commit 20e03d702e00a3e0269a1d6f9549c2e370492054 ] commit 3f1e782998 ("riscv: add ASID-based tlbflushing methods") added calls to the sfence.vma instruction with rs2 != x0. These single-ASID instruction variants are also affected by SiFive errata CIP-1200. Until now, the errata workaround was not needed for the single-ASID sfence.vma variants, because they were only used when the ASID allocator was enabled, and the affected SiFive platforms do not support multiple ASIDs. However, we are going to start using those sfence.vma variants regardless of ASID support, so now we need alternatives covering them. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-8-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-07-11 12:49:06 +02:00
..
asm	riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma	2024-07-11 12:49:06 +02:00
uapi/asm	RISC-V: Update AT_VECTOR_SIZE_ARCH for new AT_MINSIGSTKSZ	2024-04-10 16:35:58 +02:00