The SoC-FPGA reset controller driver defines NR_BANKS as 4 and uses that define
for two unrelated purposes. It is used
1. as an increment for reset line banks which are 32-bit registers with 4-byte
aligned addresses.
2. as the total number of reset line banks which together with the number of
resets per bank (32) limits the total number of useable resets to 128 and the
highest useable reset ID to 127.
This is clearly wrong as there are resets with higher IDs than 127 defined in
include/dt-bindings/reset/altr,rst-mgr.h and altr,rst-mgr-a10.h.
The patch introduces a new define BANK_INCREMENT for calculating the register
addresses as before and increases NR_BANKS to 8 for useable reset IDs up to 255.
Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
d518d9cab1