268 lines
6.1 KiB
C
268 lines
6.1 KiB
C
/*
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* TI da8xx master peripheral priority driver
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*
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* Copyright (C) 2016 BayLibre SAS
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*
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* Author:
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* Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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/*
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* REVISIT: Linux doesn't have a good framework for the kind of performance
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* knobs this driver controls. We can't use device tree properties as it deals
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* with hardware configuration rather than description. We also don't want to
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* commit to maintaining some random sysfs attributes.
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*
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* For now we just hardcode the register values for the boards that need
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* some changes (as is the case for the LCD controller on da850-lcdk - the
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* first board we support here). When linux gets an appropriate framework,
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* we'll easily convert the driver to it.
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*/
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#define DA8XX_MSTPRI0_OFFSET 0
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#define DA8XX_MSTPRI1_OFFSET 4
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#define DA8XX_MSTPRI2_OFFSET 8
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enum {
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DA8XX_MSTPRI_ARM_I = 0,
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DA8XX_MSTPRI_ARM_D,
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DA8XX_MSTPRI_UPP,
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DA8XX_MSTPRI_SATA,
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DA8XX_MSTPRI_PRU0,
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DA8XX_MSTPRI_PRU1,
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DA8XX_MSTPRI_EDMA30TC0,
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DA8XX_MSTPRI_EDMA30TC1,
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DA8XX_MSTPRI_EDMA31TC0,
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DA8XX_MSTPRI_VPIF_DMA_0,
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DA8XX_MSTPRI_VPIF_DMA_1,
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DA8XX_MSTPRI_EMAC,
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DA8XX_MSTPRI_USB0CFG,
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DA8XX_MSTPRI_USB0CDMA,
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DA8XX_MSTPRI_UHPI,
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DA8XX_MSTPRI_USB1,
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DA8XX_MSTPRI_LCDC,
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};
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struct da8xx_mstpri_descr {
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int reg;
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int shift;
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int mask;
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};
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static const struct da8xx_mstpri_descr da8xx_mstpri_priority_list[] = {
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[DA8XX_MSTPRI_ARM_I] = {
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.reg = DA8XX_MSTPRI0_OFFSET,
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.shift = 0,
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.mask = 0x0000000f,
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},
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[DA8XX_MSTPRI_ARM_D] = {
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.reg = DA8XX_MSTPRI0_OFFSET,
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.shift = 4,
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.mask = 0x000000f0,
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},
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[DA8XX_MSTPRI_UPP] = {
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.reg = DA8XX_MSTPRI0_OFFSET,
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.shift = 16,
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.mask = 0x000f0000,
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},
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[DA8XX_MSTPRI_SATA] = {
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.reg = DA8XX_MSTPRI0_OFFSET,
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.shift = 20,
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.mask = 0x00f00000,
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},
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[DA8XX_MSTPRI_PRU0] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 0,
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.mask = 0x0000000f,
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},
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[DA8XX_MSTPRI_PRU1] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 4,
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.mask = 0x000000f0,
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},
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[DA8XX_MSTPRI_EDMA30TC0] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 8,
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.mask = 0x00000f00,
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},
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[DA8XX_MSTPRI_EDMA30TC1] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 12,
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.mask = 0x0000f000,
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},
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[DA8XX_MSTPRI_EDMA31TC0] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 16,
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.mask = 0x000f0000,
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},
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[DA8XX_MSTPRI_VPIF_DMA_0] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 24,
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.mask = 0x0f000000,
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},
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[DA8XX_MSTPRI_VPIF_DMA_1] = {
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.reg = DA8XX_MSTPRI1_OFFSET,
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.shift = 28,
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.mask = 0xf0000000,
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},
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[DA8XX_MSTPRI_EMAC] = {
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.reg = DA8XX_MSTPRI2_OFFSET,
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.shift = 0,
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.mask = 0x0000000f,
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},
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[DA8XX_MSTPRI_USB0CFG] = {
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.reg = DA8XX_MSTPRI2_OFFSET,
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.shift = 8,
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.mask = 0x00000f00,
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},
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[DA8XX_MSTPRI_USB0CDMA] = {
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.reg = DA8XX_MSTPRI2_OFFSET,
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.shift = 12,
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.mask = 0x0000f000,
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},
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[DA8XX_MSTPRI_UHPI] = {
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.reg = DA8XX_MSTPRI2_OFFSET,
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.shift = 20,
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.mask = 0x00f00000,
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},
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[DA8XX_MSTPRI_USB1] = {
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.reg = DA8XX_MSTPRI2_OFFSET,
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.shift = 24,
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.mask = 0x0f000000,
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},
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[DA8XX_MSTPRI_LCDC] = {
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.reg = DA8XX_MSTPRI2_OFFSET,
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.shift = 28,
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.mask = 0xf0000000,
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},
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};
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struct da8xx_mstpri_priority {
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int which;
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u32 val;
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};
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struct da8xx_mstpri_board_priorities {
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const char *board;
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const struct da8xx_mstpri_priority *priorities;
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size_t numprio;
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};
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/*
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* Default memory settings of da850 do not meet the throughput/latency
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* requirements of tilcdc. This results in the image displayed being
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* incorrect and the following warning being displayed by the LCDC
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* drm driver:
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*
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* tilcdc da8xx_lcdc.0: tilcdc_crtc_irq(0x00000020): FIFO underfow
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*/
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static const struct da8xx_mstpri_priority da850_lcdk_priorities[] = {
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{
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.which = DA8XX_MSTPRI_LCDC,
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.val = 0,
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},
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{
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.which = DA8XX_MSTPRI_EDMA30TC1,
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.val = 0,
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},
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{
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.which = DA8XX_MSTPRI_EDMA30TC0,
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.val = 1,
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},
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};
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static const struct da8xx_mstpri_board_priorities da8xx_mstpri_board_confs[] = {
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{
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.board = "ti,da850-lcdk",
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.priorities = da850_lcdk_priorities,
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.numprio = ARRAY_SIZE(da850_lcdk_priorities),
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},
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};
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static const struct da8xx_mstpri_board_priorities *
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da8xx_mstpri_get_board_prio(void)
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{
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const struct da8xx_mstpri_board_priorities *board_prio;
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int i;
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for (i = 0; i < ARRAY_SIZE(da8xx_mstpri_board_confs); i++) {
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board_prio = &da8xx_mstpri_board_confs[i];
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if (of_machine_is_compatible(board_prio->board))
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return board_prio;
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}
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return NULL;
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}
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static int da8xx_mstpri_probe(struct platform_device *pdev)
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{
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const struct da8xx_mstpri_board_priorities *prio_list;
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const struct da8xx_mstpri_descr *prio_descr;
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const struct da8xx_mstpri_priority *prio;
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struct device *dev = &pdev->dev;
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struct resource *res;
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void __iomem *mstpri;
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u32 reg;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mstpri = devm_ioremap_resource(dev, res);
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if (IS_ERR(mstpri)) {
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dev_err(dev, "unable to map MSTPRI registers\n");
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return PTR_ERR(mstpri);
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}
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prio_list = da8xx_mstpri_get_board_prio();
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if (!prio_list) {
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dev_err(dev, "no master priorities defined for this board\n");
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return -EINVAL;
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}
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for (i = 0; i < prio_list->numprio; i++) {
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prio = &prio_list->priorities[i];
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prio_descr = &da8xx_mstpri_priority_list[prio->which];
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if (prio_descr->reg + sizeof(u32) > resource_size(res)) {
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dev_warn(dev, "register offset out of range\n");
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continue;
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}
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reg = readl(mstpri + prio_descr->reg);
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reg &= ~prio_descr->mask;
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reg |= prio->val << prio_descr->shift;
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writel(reg, mstpri + prio_descr->reg);
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}
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return 0;
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}
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static const struct of_device_id da8xx_mstpri_of_match[] = {
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{ .compatible = "ti,da850-mstpri", },
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{ },
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};
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static struct platform_driver da8xx_mstpri_driver = {
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.probe = da8xx_mstpri_probe,
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.driver = {
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.name = "da8xx-mstpri",
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.of_match_table = da8xx_mstpri_of_match,
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},
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};
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module_platform_driver(da8xx_mstpri_driver);
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MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
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MODULE_DESCRIPTION("TI da8xx master peripheral priority driver");
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MODULE_LICENSE("GPL v2");
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