541 lines
15 KiB
C
541 lines
15 KiB
C
/*
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* Support for Celleb PCI-Express.
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*
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* (C) Copyright 2007-2008 TOSHIBA CORPORATION
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/iommu.h>
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#include <asm/byteorder.h>
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#include "celleb_scc.h"
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#include "celleb_pci.h"
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#define PEX_IN(base, off) in_be32((void __iomem *)(base) + (off))
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#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))
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static void scc_pciex_io_flush(struct iowa_bus *bus)
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{
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(void)PEX_IN(bus->phb->cfg_addr, PEXDMRDEN0);
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}
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/*
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* Memory space access to device on PCIEX
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*/
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#define PCIEX_MMIO_READ(name, ret) \
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static ret scc_pciex_##name(const PCI_IO_ADDR addr) \
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{ \
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ret val = __do_##name(addr); \
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scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
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return val; \
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}
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#define PCIEX_MMIO_READ_STR(name) \
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static void scc_pciex_##name(const PCI_IO_ADDR addr, void *buf, \
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unsigned long count) \
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{ \
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__do_##name(addr, buf, count); \
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scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
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}
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PCIEX_MMIO_READ(readb, u8)
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PCIEX_MMIO_READ(readw, u16)
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PCIEX_MMIO_READ(readl, u32)
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PCIEX_MMIO_READ(readq, u64)
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PCIEX_MMIO_READ(readw_be, u16)
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PCIEX_MMIO_READ(readl_be, u32)
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PCIEX_MMIO_READ(readq_be, u64)
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PCIEX_MMIO_READ_STR(readsb)
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PCIEX_MMIO_READ_STR(readsw)
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PCIEX_MMIO_READ_STR(readsl)
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static void scc_pciex_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
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unsigned long n)
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{
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__do_memcpy_fromio(dest, src, n);
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scc_pciex_io_flush(iowa_mem_find_bus(src));
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}
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/*
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* I/O port access to devices on PCIEX.
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*/
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static inline unsigned long get_bus_address(struct pci_controller *phb,
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unsigned long port)
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{
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return port - ((unsigned long)(phb->io_base_virt) - _IO_BASE);
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}
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static u32 scc_pciex_read_port(struct pci_controller *phb,
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unsigned long port, int size)
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{
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unsigned int byte_enable;
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unsigned int cmd, shift;
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unsigned long addr;
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u32 data, ret;
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BUG_ON(((port & 0x3ul) + size) > 4);
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addr = get_bus_address(phb, port);
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shift = addr & 0x3ul;
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byte_enable = ((1 << size) - 1) << shift;
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cmd = PEXDCMND_IO_READ | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
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PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
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PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
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data = PEX_IN(phb->cfg_addr, PEXDRDATA);
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ret = (data >> (shift * 8)) & (0xFFFFFFFF >> ((4 - size) * 8));
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pr_debug("PCIEX:PIO READ:port=0x%lx, addr=0x%lx, size=%d, be=%x,"
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" cmd=%x, data=%x, ret=%x\n", port, addr, size, byte_enable,
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cmd, data, ret);
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return ret;
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}
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static void scc_pciex_write_port(struct pci_controller *phb,
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unsigned long port, int size, u32 val)
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{
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unsigned int byte_enable;
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unsigned int cmd, shift;
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unsigned long addr;
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u32 data;
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BUG_ON(((port & 0x3ul) + size) > 4);
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addr = get_bus_address(phb, port);
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shift = addr & 0x3ul;
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byte_enable = ((1 << size) - 1) << shift;
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cmd = PEXDCMND_IO_WRITE | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
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data = (val & (0xFFFFFFFF >> (4 - size) * 8)) << (shift * 8);
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PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
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PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
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PEX_OUT(phb->cfg_addr, PEXDWDATA, data);
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pr_debug("PCIEX:PIO WRITE:port=0x%lx, addr=%lx, size=%d, val=%x,"
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" be=%x, cmd=%x, data=%x\n", port, addr, size, val,
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byte_enable, cmd, data);
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}
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static u8 __scc_pciex_inb(struct pci_controller *phb, unsigned long port)
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{
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return (u8)scc_pciex_read_port(phb, port, 1);
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}
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static u16 __scc_pciex_inw(struct pci_controller *phb, unsigned long port)
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{
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u32 data;
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if ((port & 0x3ul) < 3)
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data = scc_pciex_read_port(phb, port, 2);
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else {
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u32 d1 = scc_pciex_read_port(phb, port, 1);
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u32 d2 = scc_pciex_read_port(phb, port + 1, 1);
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data = d1 | (d2 << 8);
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}
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return (u16)data;
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}
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static u32 __scc_pciex_inl(struct pci_controller *phb, unsigned long port)
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{
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unsigned int mod = port & 0x3ul;
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u32 data;
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if (mod == 0)
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data = scc_pciex_read_port(phb, port, 4);
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else {
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u32 d1 = scc_pciex_read_port(phb, port, 4 - mod);
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u32 d2 = scc_pciex_read_port(phb, port + 1, mod);
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data = d1 | (d2 << (mod * 8));
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}
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return data;
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}
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static void __scc_pciex_outb(struct pci_controller *phb,
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u8 val, unsigned long port)
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{
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scc_pciex_write_port(phb, port, 1, (u32)val);
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}
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static void __scc_pciex_outw(struct pci_controller *phb,
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u16 val, unsigned long port)
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{
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if ((port & 0x3ul) < 3)
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scc_pciex_write_port(phb, port, 2, (u32)val);
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else {
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u32 d1 = val & 0x000000FF;
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u32 d2 = (val & 0x0000FF00) >> 8;
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scc_pciex_write_port(phb, port, 1, d1);
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scc_pciex_write_port(phb, port + 1, 1, d2);
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}
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}
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static void __scc_pciex_outl(struct pci_controller *phb,
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u32 val, unsigned long port)
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{
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unsigned int mod = port & 0x3ul;
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if (mod == 0)
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scc_pciex_write_port(phb, port, 4, val);
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else {
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u32 d1 = val & (0xFFFFFFFFul >> (mod * 8));
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u32 d2 = val >> ((4 - mod) * 8);
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scc_pciex_write_port(phb, port, 4 - mod, d1);
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scc_pciex_write_port(phb, port + 1, mod, d2);
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}
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}
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#define PCIEX_PIO_FUNC(size, name) \
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static u##size scc_pciex_in##name(unsigned long port) \
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{ \
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struct iowa_bus *bus = iowa_pio_find_bus(port); \
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u##size data = __scc_pciex_in##name(bus->phb, port); \
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scc_pciex_io_flush(bus); \
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return data; \
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} \
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static void scc_pciex_ins##name(unsigned long p, void *b, unsigned long c) \
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{ \
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struct iowa_bus *bus = iowa_pio_find_bus(p); \
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__le##size *dst = b; \
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for (; c != 0; c--, dst++) \
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*dst = cpu_to_le##size(__scc_pciex_in##name(bus->phb, p)); \
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scc_pciex_io_flush(bus); \
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} \
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static void scc_pciex_out##name(u##size val, unsigned long port) \
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{ \
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struct iowa_bus *bus = iowa_pio_find_bus(port); \
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__scc_pciex_out##name(bus->phb, val, port); \
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} \
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static void scc_pciex_outs##name(unsigned long p, const void *b, \
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unsigned long c) \
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{ \
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struct iowa_bus *bus = iowa_pio_find_bus(p); \
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const __le##size *src = b; \
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for (; c != 0; c--, src++) \
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__scc_pciex_out##name(bus->phb, le##size##_to_cpu(*src), p); \
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}
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#define __le8 u8
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#define cpu_to_le8(x) (x)
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#define le8_to_cpu(x) (x)
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PCIEX_PIO_FUNC(8, b)
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PCIEX_PIO_FUNC(16, w)
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PCIEX_PIO_FUNC(32, l)
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static struct ppc_pci_io scc_pciex_ops = {
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.readb = scc_pciex_readb,
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.readw = scc_pciex_readw,
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.readl = scc_pciex_readl,
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.readq = scc_pciex_readq,
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.readw_be = scc_pciex_readw_be,
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.readl_be = scc_pciex_readl_be,
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.readq_be = scc_pciex_readq_be,
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.readsb = scc_pciex_readsb,
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.readsw = scc_pciex_readsw,
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.readsl = scc_pciex_readsl,
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.memcpy_fromio = scc_pciex_memcpy_fromio,
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.inb = scc_pciex_inb,
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.inw = scc_pciex_inw,
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.inl = scc_pciex_inl,
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.outb = scc_pciex_outb,
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.outw = scc_pciex_outw,
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.outl = scc_pciex_outl,
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.insb = scc_pciex_insb,
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.insw = scc_pciex_insw,
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.insl = scc_pciex_insl,
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.outsb = scc_pciex_outsb,
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.outsw = scc_pciex_outsw,
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.outsl = scc_pciex_outsl,
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};
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static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data)
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{
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dma_addr_t dummy_page_da;
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void *dummy_page_va;
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dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (!dummy_page_va) {
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pr_err("PCIEX:Alloc dummy_page_va failed\n");
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return -1;
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}
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dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
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PAGE_SIZE, DMA_FROM_DEVICE);
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if (dma_mapping_error(bus->phb->parent, dummy_page_da)) {
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pr_err("PCIEX:Map dummy page failed.\n");
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kfree(dummy_page_va);
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return -1;
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}
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PEX_OUT(bus->phb->cfg_addr, PEXDMRDADR0, dummy_page_da);
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return 0;
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}
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/*
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* config space access
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*/
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#define MK_PEXDADRS(bus_no, dev_no, func_no, addr) \
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((uint32_t)(((addr) & ~0x3UL) | \
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((bus_no) << PEXDADRS_BUSNO_SHIFT) | \
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((dev_no) << PEXDADRS_DEVNO_SHIFT) | \
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((func_no) << PEXDADRS_FUNCNO_SHIFT)))
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#define MK_PEXDCMND_BYTE_EN(addr, size) \
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((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
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#define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size))
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static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
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uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
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uint64_t off, uint64_t size)
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{
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uint32_t ret;
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uint32_t addr, cmd;
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addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
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cmd = MK_PEXDCMND(PEXDCMND_CONFIG_READ, off, size);
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PEX_OUT(base, PEXDADRS, addr);
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PEX_OUT(base, PEXDCMND, cmd);
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ret = (PEX_IN(base, PEXDRDATA)
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>> ((off & (4-size)) * 8)) & ((0x1 << (size * 8)) - 1);
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return ret;
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}
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static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
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uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
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uint32_t data)
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{
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uint32_t addr, cmd;
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addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
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cmd = MK_PEXDCMND(PEXDCMND_CONFIG_WRITE, off, size);
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PEX_OUT(base, PEXDADRS, addr);
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PEX_OUT(base, PEXDCMND, cmd);
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PEX_OUT(base, PEXDWDATA,
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(data & ((0x1 << (size * 8)) - 1)) << ((off & (4-size)) * 8));
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}
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#define MK_PEXCADRS_BYTE_EN(off, len) \
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((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
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#define MK_PEXCADRS(cmd, addr, size) \
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((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3))
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static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
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uint32_t where, uint32_t size)
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{
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PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
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return (PEX_IN(base, PEXCRDATA)
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>> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
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}
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static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
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uint32_t size, uint32_t val)
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{
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uint32_t data;
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data = (val & ((0x1 << (size * 8)) - 1)) << ((where & (4 - size)) * 8);
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PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_WRITE, where, size));
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PEX_OUT(base, PEXCWDATA, data);
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}
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/* Interfaces */
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/* Note: Work-around
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* On SCC PCIEXC, one device is seen on all 32 dev_no.
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* As SCC PCIEXC can have only one device on the bus, we look only one dev_no.
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* (dev_no = 1)
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*/
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static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, unsigned int *val)
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{
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struct pci_controller *phb = pci_bus_to_host(bus);
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if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if (bus->number == 0 && PCI_SLOT(devfn) == 0)
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*val = config_read_pciex_rc(phb->cfg_addr, where, size);
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else
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*val = config_read_pciex_dev(phb->cfg_addr, bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, unsigned int val)
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{
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struct pci_controller *phb = pci_bus_to_host(bus);
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if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == 0 && PCI_SLOT(devfn) == 0)
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config_write_pciex_rc(phb->cfg_addr, where, size, val);
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else
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config_write_pciex_dev(phb->cfg_addr, bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops scc_pciex_pci_ops = {
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scc_pciex_read_config,
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scc_pciex_write_config,
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};
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static void pciex_clear_intr_all(unsigned int __iomem *base)
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{
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PEX_OUT(base, PEXAERRSTS, 0xffffffff);
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PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
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PEX_OUT(base, PEXINTSTS, 0xffffffff);
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}
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#if 0
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static void pciex_disable_intr_all(unsigned int *base)
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{
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PEX_OUT(base, PEXINTMASK, 0x0);
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PEX_OUT(base, PEXAERRMASK, 0x0);
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PEX_OUT(base, PEXPRERRMASK, 0x0);
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PEX_OUT(base, PEXVDMASK, 0x0);
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}
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#endif
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static void pciex_enable_intr_all(unsigned int __iomem *base)
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{
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PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
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PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
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PEX_OUT(base, PEXPRERRMASK, 0x0001010f);
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PEX_OUT(base, PEXVDMASK, 0x00000001);
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}
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static void pciex_check_status(unsigned int __iomem *base)
|
|
{
|
|
uint32_t err = 0;
|
|
uint32_t intsts, aerr, prerr, rcvcp, lenerr;
|
|
uint32_t maea, maec;
|
|
|
|
intsts = PEX_IN(base, PEXINTSTS);
|
|
aerr = PEX_IN(base, PEXAERRSTS);
|
|
prerr = PEX_IN(base, PEXPRERRSTS);
|
|
rcvcp = PEX_IN(base, PEXRCVCPLIDA);
|
|
lenerr = PEX_IN(base, PEXLENERRIDA);
|
|
|
|
if (intsts || aerr || prerr || rcvcp || lenerr)
|
|
err = 1;
|
|
|
|
pr_info("PCEXC interrupt!!\n");
|
|
pr_info("PEXINTSTS :0x%08x\n", intsts);
|
|
pr_info("PEXAERRSTS :0x%08x\n", aerr);
|
|
pr_info("PEXPRERRSTS :0x%08x\n", prerr);
|
|
pr_info("PEXRCVCPLIDA :0x%08x\n", rcvcp);
|
|
pr_info("PEXLENERRIDA :0x%08x\n", lenerr);
|
|
|
|
/* print detail of Protection Error */
|
|
if (intsts & 0x00004000) {
|
|
uint32_t i, n;
|
|
for (i = 0; i < 4; i++) {
|
|
n = 1 << i;
|
|
if (prerr & n) {
|
|
maea = PEX_IN(base, PEXMAEA(i));
|
|
maec = PEX_IN(base, PEXMAEC(i));
|
|
pr_info("PEXMAEC%d :0x%08x\n", i, maec);
|
|
pr_info("PEXMAEA%d :0x%08x\n", i, maea);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (err)
|
|
pciex_clear_intr_all(base);
|
|
}
|
|
|
|
static irqreturn_t pciex_handle_internal_irq(int irq, void *dev_id)
|
|
{
|
|
struct pci_controller *phb = dev_id;
|
|
|
|
pr_debug("PCIEX:pciex_handle_internal_irq(irq=%d)\n", irq);
|
|
|
|
BUG_ON(phb->cfg_addr == NULL);
|
|
|
|
pciex_check_status(phb->cfg_addr);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static __init int celleb_setup_pciex(struct device_node *node,
|
|
struct pci_controller *phb)
|
|
{
|
|
struct resource r;
|
|
struct of_irq oirq;
|
|
int virq;
|
|
|
|
/* SMMIO registers; used inside this file */
|
|
if (of_address_to_resource(node, 0, &r)) {
|
|
pr_err("PCIEXC:Failed to get config resource.\n");
|
|
return 1;
|
|
}
|
|
phb->cfg_addr = ioremap(r.start, r.end - r.start + 1);
|
|
if (!phb->cfg_addr) {
|
|
pr_err("PCIEXC:Failed to remap SMMIO region.\n");
|
|
return 1;
|
|
}
|
|
|
|
/* Not use cfg_data, cmd and data regs are near address reg */
|
|
phb->cfg_data = NULL;
|
|
|
|
/* set pci_ops */
|
|
phb->ops = &scc_pciex_pci_ops;
|
|
|
|
/* internal interrupt handler */
|
|
if (of_irq_map_one(node, 1, &oirq)) {
|
|
pr_err("PCIEXC:Failed to map irq\n");
|
|
goto error;
|
|
}
|
|
virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
|
|
oirq.size);
|
|
if (request_irq(virq, pciex_handle_internal_irq,
|
|
IRQF_DISABLED, "pciex", (void *)phb)) {
|
|
pr_err("PCIEXC:Failed to request irq\n");
|
|
goto error;
|
|
}
|
|
|
|
/* enable all interrupts */
|
|
pciex_clear_intr_all(phb->cfg_addr);
|
|
pciex_enable_intr_all(phb->cfg_addr);
|
|
/* MSI: TBD */
|
|
|
|
return 0;
|
|
|
|
error:
|
|
phb->cfg_data = NULL;
|
|
if (phb->cfg_addr)
|
|
iounmap(phb->cfg_addr);
|
|
phb->cfg_addr = NULL;
|
|
return 1;
|
|
}
|
|
|
|
struct celleb_phb_spec celleb_pciex_spec __initdata = {
|
|
.setup = celleb_setup_pciex,
|
|
.ops = &scc_pciex_ops,
|
|
.iowa_init = &scc_pciex_iowa_init,
|
|
};
|