209 lines
9.4 KiB
C
209 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Register Base Addresses */
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#define XRS_DEVICE_ID_BASE 0x0
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#define XRS_GPIO_BASE 0x10000
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#define XRS_PORT_OFFSET 0x10000
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#define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x))
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#define XRS_RTC_BASE 0x280000
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#define XRS_TS_OFFSET 0x8000
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#define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x))
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#define XRS_SWITCH_CONF_BASE 0x300000
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/* Device Identification Registers */
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#define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0)
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#define XRS_DEV_ID1 (XRS_DEVICE_ID_BASE + 2)
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#define XRS_INT_ID0 (XRS_DEVICE_ID_BASE + 4)
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#define XRS_INT_ID1 (XRS_DEVICE_ID_BASE + 6)
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#define XRS_REV_ID (XRS_DEVICE_ID_BASE + 8)
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/* GPIO Registers */
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#define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000)
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#define XRS_INPUT_STATUS0 (XRS_GPIO_BASE + 0x1002)
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#define XRS_CONFIG1 (XRS_GPIO_BASE + 0x1004)
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#define XRS_INPUT_STATUS1 (XRS_GPIO_BASE + 0x1006)
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#define XRS_CONFIG2 (XRS_GPIO_BASE + 0x1008)
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#define XRS_INPUT_STATUS2 (XRS_GPIO_BASE + 0x100a)
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/* Port Configuration Registers */
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#define XRS_PORT_GEN_BASE(x) (XRS_PORT_BASE(x) + 0x0)
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#define XRS_PORT_HSR_BASE(x) (XRS_PORT_BASE(x) + 0x2000)
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#define XRS_PORT_PTP_BASE(x) (XRS_PORT_BASE(x) + 0x4000)
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#define XRS_PORT_CNT_BASE(x) (XRS_PORT_BASE(x) + 0x6000)
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#define XRS_PORT_IPO_BASE(x) (XRS_PORT_BASE(x) + 0x8000)
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/* Port Configuration Registers - General and State */
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#define XRS_PORT_STATE(x) (XRS_PORT_GEN_BASE(x) + 0x0)
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#define XRS_PORT_FORWARDING 0
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#define XRS_PORT_LEARNING 1
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#define XRS_PORT_DISABLED 2
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#define XRS_PORT_MODE_NORMAL 0
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#define XRS_PORT_MODE_MANAGEMENT 1
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#define XRS_PORT_SPEED_1000 0x12
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#define XRS_PORT_SPEED_100 0x20
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#define XRS_PORT_SPEED_10 0x30
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#define XRS_PORT_VLAN(x) (XRS_PORT_GEN_BASE(x) + 0x10)
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#define XRS_PORT_VLAN0_MAPPING(x) (XRS_PORT_GEN_BASE(x) + 0x12)
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#define XRS_PORT_FWD_MASK(x) (XRS_PORT_GEN_BASE(x) + 0x14)
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#define XRS_PORT_VLAN_PRIO(x) (XRS_PORT_GEN_BASE(x) + 0x16)
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/* Port Configuration Registers - HSR/PRP */
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#define XRS_HSR_CFG(x) (XRS_PORT_HSR_BASE(x) + 0x0)
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#define XRS_HSR_CFG_HSR_PRP BIT(0)
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#define XRS_HSR_CFG_HSR 0
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#define XRS_HSR_CFG_PRP BIT(8)
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#define XRS_HSR_CFG_LANID_A 0
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#define XRS_HSR_CFG_LANID_B BIT(10)
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/* Port Configuration Registers - PTP */
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#define XRS_PTP_RX_SYNC_DELAY_NS_LO(x) (XRS_PORT_PTP_BASE(x) + 0x2)
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#define XRS_PTP_RX_SYNC_DELAY_NS_HI(x) (XRS_PORT_PTP_BASE(x) + 0x4)
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#define XRS_PTP_RX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0xa)
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#define XRS_PTP_TX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0x12)
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/* Port Configuration Registers - Counter */
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#define XRS_CNT_CTRL(x) (XRS_PORT_CNT_BASE(x) + 0x0)
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#define XRS_RX_GOOD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x200)
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#define XRS_RX_GOOD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x202)
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#define XRS_RX_BAD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x204)
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#define XRS_RX_BAD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x206)
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#define XRS_RX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x208)
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#define XRS_RX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x20a)
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#define XRS_RX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x20c)
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#define XRS_RX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x20e)
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#define XRS_RX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x210)
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#define XRS_RX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x212)
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#define XRS_RX_UNDERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x214)
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#define XRS_RX_UNDERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x216)
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#define XRS_RX_FRAGMENTS_L (XRS_PORT_CNT_BASE(0) + 0x218)
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#define XRS_RX_FRAGMENTS_H (XRS_PORT_CNT_BASE(0) + 0x21a)
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#define XRS_RX_OVERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x21c)
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#define XRS_RX_OVERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x21e)
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#define XRS_RX_JABBER_L (XRS_PORT_CNT_BASE(0) + 0x220)
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#define XRS_RX_JABBER_H (XRS_PORT_CNT_BASE(0) + 0x222)
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#define XRS_RX_ERR_L (XRS_PORT_CNT_BASE(0) + 0x224)
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#define XRS_RX_ERR_H (XRS_PORT_CNT_BASE(0) + 0x226)
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#define XRS_RX_CRC_L (XRS_PORT_CNT_BASE(0) + 0x228)
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#define XRS_RX_CRC_H (XRS_PORT_CNT_BASE(0) + 0x22a)
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#define XRS_RX_64_L (XRS_PORT_CNT_BASE(0) + 0x22c)
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#define XRS_RX_64_H (XRS_PORT_CNT_BASE(0) + 0x22e)
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#define XRS_RX_65_127_L (XRS_PORT_CNT_BASE(0) + 0x230)
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#define XRS_RX_65_127_H (XRS_PORT_CNT_BASE(0) + 0x232)
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#define XRS_RX_128_255_L (XRS_PORT_CNT_BASE(0) + 0x234)
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#define XRS_RX_128_255_H (XRS_PORT_CNT_BASE(0) + 0x236)
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#define XRS_RX_256_511_L (XRS_PORT_CNT_BASE(0) + 0x238)
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#define XRS_RX_256_511_H (XRS_PORT_CNT_BASE(0) + 0x23a)
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#define XRS_RX_512_1023_L (XRS_PORT_CNT_BASE(0) + 0x23c)
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#define XRS_RX_512_1023_H (XRS_PORT_CNT_BASE(0) + 0x23e)
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#define XRS_RX_1024_1536_L (XRS_PORT_CNT_BASE(0) + 0x240)
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#define XRS_RX_1024_1536_H (XRS_PORT_CNT_BASE(0) + 0x242)
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#define XRS_RX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x244)
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#define XRS_RX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x246)
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#define XRS_RX_WRONGLAN_L (XRS_PORT_CNT_BASE(0) + 0x248)
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#define XRS_RX_WRONGLAN_H (XRS_PORT_CNT_BASE(0) + 0x24a)
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#define XRS_RX_DUPLICATE_L (XRS_PORT_CNT_BASE(0) + 0x24c)
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#define XRS_RX_DUPLICATE_H (XRS_PORT_CNT_BASE(0) + 0x24e)
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#define XRS_TX_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x280)
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#define XRS_TX_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x282)
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#define XRS_TX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x284)
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#define XRS_TX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x286)
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#define XRS_TX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x288)
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#define XRS_TX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x28a)
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#define XRS_TX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x28c)
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#define XRS_TX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x28e)
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#define XRS_TX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x290)
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#define XRS_TX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x292)
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#define XRS_PRIQ_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c0)
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#define XRS_PRIQ_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c2)
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#define XRS_EARLY_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c4)
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#define XRS_EARLY_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c6)
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/* Port Configuration Registers - Inbound Policy 0 - 15 */
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#define XRS_ETH_ADDR_CFG(x, p) (XRS_PORT_IPO_BASE(x) + \
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(p) * 0x20 + 0x0)
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#define XRS_ETH_ADDR_FWD_ALLOW(x, p) (XRS_PORT_IPO_BASE(x) + \
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(p) * 0x20 + 0x2)
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#define XRS_ETH_ADDR_FWD_MIRROR(x, p) (XRS_PORT_IPO_BASE(x) + \
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(p) * 0x20 + 0x4)
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#define XRS_ETH_ADDR_0(x, p) (XRS_PORT_IPO_BASE(x) + \
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(p) * 0x20 + 0x8)
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#define XRS_ETH_ADDR_1(x, p) (XRS_PORT_IPO_BASE(x) + \
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(p) * 0x20 + 0xa)
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#define XRS_ETH_ADDR_2(x, p) (XRS_PORT_IPO_BASE(x) + \
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(p) * 0x20 + 0xc)
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/* RTC Registers */
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#define XRS_CUR_NSEC0 (XRS_RTC_BASE + 0x1004)
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#define XRS_CUR_NSEC1 (XRS_RTC_BASE + 0x1006)
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#define XRS_CUR_SEC0 (XRS_RTC_BASE + 0x1008)
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#define XRS_CUR_SEC1 (XRS_RTC_BASE + 0x100a)
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#define XRS_CUR_SEC2 (XRS_RTC_BASE + 0x100c)
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#define XRS_TIME_CC0 (XRS_RTC_BASE + 0x1010)
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#define XRS_TIME_CC1 (XRS_RTC_BASE + 0x1012)
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#define XRS_TIME_CC2 (XRS_RTC_BASE + 0x1014)
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#define XRS_STEP_SIZE0 (XRS_RTC_BASE + 0x1020)
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#define XRS_STEP_SIZE1 (XRS_RTC_BASE + 0x1022)
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#define XRS_STEP_SIZE2 (XRS_RTC_BASE + 0x1024)
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#define XRS_ADJUST_NSEC0 (XRS_RTC_BASE + 0x1034)
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#define XRS_ADJUST_NSEC1 (XRS_RTC_BASE + 0x1036)
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#define XRS_ADJUST_SEC0 (XRS_RTC_BASE + 0x1038)
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#define XRS_ADJUST_SEC1 (XRS_RTC_BASE + 0x103a)
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#define XRS_ADJUST_SEC2 (XRS_RTC_BASE + 0x103c)
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#define XRS_TIME_CMD (XRS_RTC_BASE + 0x1040)
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/* Time Stamper Registers */
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#define XRS_TS_CTRL(x) (XRS_TS_BASE(x) + 0x1000)
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#define XRS_TS_INT_MASK(x) (XRS_TS_BASE(x) + 0x1008)
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#define XRS_TS_INT_STATUS(x) (XRS_TS_BASE(x) + 0x1010)
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#define XRS_TS_NSEC0(x) (XRS_TS_BASE(x) + 0x1104)
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#define XRS_TS_NSEC1(x) (XRS_TS_BASE(x) + 0x1106)
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#define XRS_TS_SEC0(x) (XRS_TS_BASE(x) + 0x1108)
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#define XRS_TS_SEC1(x) (XRS_TS_BASE(x) + 0x110a)
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#define XRS_TS_SEC2(x) (XRS_TS_BASE(x) + 0x110c)
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#define XRS_PNCT0(x) (XRS_TS_BASE(x) + 0x1110)
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#define XRS_PNCT1(x) (XRS_TS_BASE(x) + 0x1112)
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/* Switch Configuration Registers */
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#define XRS_SWITCH_GEN_BASE (XRS_SWITCH_CONF_BASE + 0x0)
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#define XRS_SWITCH_TS_BASE (XRS_SWITCH_CONF_BASE + 0x2000)
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#define XRS_SWITCH_VLAN_BASE (XRS_SWITCH_CONF_BASE + 0x4000)
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/* Switch Configuration Registers - General */
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#define XRS_GENERAL (XRS_SWITCH_GEN_BASE + 0x10)
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#define XRS_GENERAL_TIME_TRAILER BIT(9)
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#define XRS_GENERAL_MOD_SYNC BIT(10)
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#define XRS_GENERAL_CUT_THRU BIT(13)
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#define XRS_GENERAL_CLR_MAC_TBL BIT(14)
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#define XRS_GENERAL_RESET BIT(15)
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#define XRS_MT_CLEAR_MASK (XRS_SWITCH_GEN_BASE + 0x12)
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#define XRS_ADDRESS_AGING (XRS_SWITCH_GEN_BASE + 0x20)
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#define XRS_TS_CTRL_TX (XRS_SWITCH_GEN_BASE + 0x28)
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#define XRS_TS_CTRL_RX (XRS_SWITCH_GEN_BASE + 0x2a)
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#define XRS_INT_MASK (XRS_SWITCH_GEN_BASE + 0x2c)
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#define XRS_INT_STATUS (XRS_SWITCH_GEN_BASE + 0x2e)
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#define XRS_MAC_TABLE0 (XRS_SWITCH_GEN_BASE + 0x200)
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#define XRS_MAC_TABLE1 (XRS_SWITCH_GEN_BASE + 0x202)
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#define XRS_MAC_TABLE2 (XRS_SWITCH_GEN_BASE + 0x204)
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#define XRS_MAC_TABLE3 (XRS_SWITCH_GEN_BASE + 0x206)
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/* Switch Configuration Registers - Frame Timestamp */
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#define XRS_TX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x0)
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#define XRS_TX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x2)
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#define XRS_TX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x4)
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#define XRS_TX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x6)
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#define XRS_TX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
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0x2 * (h) + 0xe)
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#define XRS_RX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
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0x200)
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#define XRS_RX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
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0x202)
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#define XRS_RX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
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0x204)
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#define XRS_RX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
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0x206)
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#define XRS_RX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
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0x2 * (h) + 0xe)
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/* Switch Configuration Registers - VLAN */
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#define XRS_VLAN(v) (XRS_SWITCH_VLAN_BASE + 0x2 * (v))
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