173 lines
5.6 KiB
C
173 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 Samsung Electronics Co., Ltd.
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* Author: Marek Szyprowski <m.szyprowski@samsung.com>
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*
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* Common Clock Framework support for Exynos4412 ISP module.
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "clk.h"
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/* Exynos4x12 specific registers, which belong to ISP power domain */
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#define E4X12_DIV_ISP0 0x0300
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#define E4X12_DIV_ISP1 0x0304
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#define E4X12_GATE_ISP0 0x0800
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#define E4X12_GATE_ISP1 0x0804
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/* NOTE: Must be equal to the last clock ID increased by one */
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#define CLKS_NR_ISP (CLK_ISP_DIV_MCUISP1 + 1)
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/*
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* Support for CMU save/restore across system suspends
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*/
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static struct samsung_clk_reg_dump *exynos4x12_save_isp;
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static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
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E4X12_DIV_ISP0,
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E4X12_DIV_ISP1,
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E4X12_GATE_ISP0,
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E4X12_GATE_ISP1,
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};
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static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
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DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
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DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
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DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
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E4X12_DIV_ISP1, 4, 3),
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DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
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E4X12_DIV_ISP1, 8, 3),
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DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
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};
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static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
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GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
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GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
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GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
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GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
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GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
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GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
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GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
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GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
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GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
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GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
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GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
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0, 0),
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GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
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0, 0),
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GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
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0, 0),
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GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
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0, 0),
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GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
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0, 0),
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GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
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0, 0),
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GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
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0, 0),
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GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
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0, 0),
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GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
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0, 0),
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GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
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GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
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GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
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0, 0),
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GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
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0, 0),
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GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
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0, 0),
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GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
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0, 0),
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GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
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0, 0),
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};
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static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
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{
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struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
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samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
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ARRAY_SIZE(exynos4x12_clk_isp_save));
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return 0;
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}
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static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
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{
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struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
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samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
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ARRAY_SIZE(exynos4x12_clk_isp_save));
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return 0;
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}
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static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
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{
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struct samsung_clk_provider *ctx;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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void __iomem *reg_base;
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
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ARRAY_SIZE(exynos4x12_clk_isp_save));
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if (!exynos4x12_save_isp)
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return -ENOMEM;
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ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
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platform_set_drvdata(pdev, ctx);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
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ARRAY_SIZE(exynos4x12_isp_div_clks));
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samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
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ARRAY_SIZE(exynos4x12_isp_gate_clks));
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samsung_clk_of_add_provider(np, ctx);
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pm_runtime_put(dev);
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return 0;
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}
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static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
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{ .compatible = "samsung,exynos4412-isp-clock", },
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{ },
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};
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static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
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SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
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exynos4x12_isp_clk_resume, NULL)
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SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
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.driver = {
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.name = "exynos4x12-isp-clk",
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.of_match_table = exynos4x12_isp_clk_of_match,
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.suppress_bind_attrs = true,
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.pm = &exynos4x12_isp_pm_ops,
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},
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.probe = exynos4x12_isp_clk_probe,
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};
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static int __init exynos4x12_isp_clk_init(void)
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{
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return platform_driver_register(&exynos4x12_isp_clk_driver);
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}
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core_initcall(exynos4x12_isp_clk_init);
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