713 lines
15 KiB
C
713 lines
15 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Copyright (C) Sunplus Technology Co., Ltd.
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* All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/bitfield.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/sunplus,sp7021-clkc.h>
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/* speical div_width values for PLLTV/PLLA */
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#define DIV_TV 33
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#define DIV_A 34
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/* PLLTV parameters */
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enum {
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SEL_FRA,
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SDM_MOD,
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PH_SEL,
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NFRA,
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DIVR,
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DIVN,
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DIVM,
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P_MAX
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};
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#define MASK_SEL_FRA GENMASK(1, 1)
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#define MASK_SDM_MOD GENMASK(2, 2)
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#define MASK_PH_SEL GENMASK(4, 4)
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#define MASK_NFRA GENMASK(12, 6)
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#define MASK_DIVR GENMASK(8, 7)
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#define MASK_DIVN GENMASK(7, 0)
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#define MASK_DIVM GENMASK(14, 8)
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/* HIWORD_MASK FIELD_PREP */
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#define HWM_FIELD_PREP(mask, value) \
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({ \
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u64 _m = mask; \
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(_m << 16) | FIELD_PREP(_m, value); \
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})
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struct sp_pll {
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struct clk_hw hw;
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void __iomem *reg;
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spinlock_t lock; /* lock for reg */
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int div_shift;
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int div_width;
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int pd_bit; /* power down bit idx */
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int bp_bit; /* bypass bit idx */
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unsigned long brate; /* base rate, TODO: replace brate with muldiv */
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u32 p[P_MAX]; /* for hold PLLTV/PLLA parameters */
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};
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#define to_sp_pll(_hw) container_of(_hw, struct sp_pll, hw)
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struct sp_clk_gate_info {
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u16 reg; /* reg_index_shift */
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u16 ext_parent; /* parent is extclk */
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};
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static const struct sp_clk_gate_info sp_clk_gates[] = {
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{ 0x02 },
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{ 0x05 },
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{ 0x06 },
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{ 0x07 },
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{ 0x09 },
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{ 0x0b, 1 },
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{ 0x0f, 1 },
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{ 0x14 },
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{ 0x15 },
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{ 0x16 },
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{ 0x17 },
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{ 0x18, 1 },
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{ 0x19, 1 },
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{ 0x1a, 1 },
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{ 0x1b, 1 },
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{ 0x1c, 1 },
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{ 0x1d, 1 },
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{ 0x1e },
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{ 0x1f, 1 },
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{ 0x20 },
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{ 0x21 },
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{ 0x22 },
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{ 0x23 },
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{ 0x24 },
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{ 0x25 },
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{ 0x26 },
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{ 0x2a },
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{ 0x2b },
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{ 0x2d },
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{ 0x2e },
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{ 0x30 },
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{ 0x31 },
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{ 0x32 },
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{ 0x33 },
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{ 0x3d },
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{ 0x3e },
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{ 0x3f },
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{ 0x42 },
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{ 0x44 },
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{ 0x4b },
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{ 0x4c },
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{ 0x4d },
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{ 0x4e },
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{ 0x4f },
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{ 0x50 },
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{ 0x55 },
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{ 0x60 },
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{ 0x61 },
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{ 0x6a },
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{ 0x73 },
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{ 0x86 },
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{ 0x8a },
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{ 0x8b },
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{ 0x8d },
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{ 0x8e },
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{ 0x8f },
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{ 0x90 },
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{ 0x92 },
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{ 0x93 },
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{ 0x95 },
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{ 0x96 },
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{ 0x97 },
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{ 0x98 },
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{ 0x99 },
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};
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#define _M 1000000UL
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#define F_27M (27 * _M)
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/*********************************** PLL_TV **********************************/
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/* TODO: set proper FVCO range */
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#define FVCO_MIN (100 * _M)
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#define FVCO_MAX (200 * _M)
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#define F_MIN (FVCO_MIN / 8)
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#define F_MAX (FVCO_MAX)
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static long plltv_integer_div(struct sp_pll *clk, unsigned long freq)
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{
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/* valid m values: 27M must be divisible by m */
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static const u32 m_table[] = {
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1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, 32
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};
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u32 m, n, r;
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unsigned long fvco, nf;
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long ret;
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freq = clamp(freq, F_MIN, F_MAX);
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/* DIVR 0~3 */
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for (r = 0; r <= 3; r++) {
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fvco = freq << r;
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if (fvco <= FVCO_MAX)
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break;
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}
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/* DIVM */
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for (m = 0; m < ARRAY_SIZE(m_table); m++) {
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nf = fvco * m_table[m];
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n = nf / F_27M;
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if ((n * F_27M) == nf)
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break;
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}
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if (m >= ARRAY_SIZE(m_table)) {
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ret = -EINVAL;
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goto err_not_found;
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}
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/* save parameters */
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clk->p[SEL_FRA] = 0;
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clk->p[DIVR] = r;
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clk->p[DIVN] = n;
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clk->p[DIVM] = m_table[m];
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return freq;
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err_not_found:
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pr_err("%s: %s freq:%lu not found a valid setting\n",
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__func__, clk_hw_get_name(&clk->hw), freq);
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return ret;
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}
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/* parameters for PLLTV fractional divider */
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static const u32 pt[][5] = {
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/* conventional fractional */
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{
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1, /* factor */
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5, /* 5 * p0 (nint) */
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1, /* 1 * p0 */
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F_27M, /* F_27M / p0 */
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1, /* p0 / p2 */
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},
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/* phase rotation */
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{
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10, /* factor */
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54, /* 5.4 * p0 (nint) */
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2, /* 0.2 * p0 */
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F_27M / 10, /* F_27M / p0 */
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5, /* p0 / p2 */
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},
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};
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static const u32 sdm_mod_vals[] = { 91, 55 };
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static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
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{
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u32 m, r;
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u32 nint, nfra;
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u32 df_quotient_min = 210000000;
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u32 df_remainder_min = 0;
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unsigned long fvco, nf, f, fout = 0;
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int sdm, ph;
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freq = clamp(freq, F_MIN, F_MAX);
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/* DIVR 0~3 */
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for (r = 0; r <= 3; r++) {
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fvco = freq << r;
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if (fvco <= FVCO_MAX)
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break;
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}
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f = F_27M >> r;
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/* PH_SEL */
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for (ph = ARRAY_SIZE(pt) - 1; ph >= 0; ph--) {
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const u32 *pp = pt[ph];
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/* SDM_MOD */
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for (sdm = 0; sdm < ARRAY_SIZE(sdm_mod_vals); sdm++) {
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u32 mod = sdm_mod_vals[sdm];
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/* DIVM 1~32 */
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for (m = 1; m <= 32; m++) {
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u32 df; /* diff freq */
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u32 df_quotient, df_remainder;
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nf = fvco * m;
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nint = nf / pp[3];
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if (nint < pp[1])
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continue;
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if (nint > pp[1])
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break;
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nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
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if (nfra) {
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u32 df0 = f * (nint + pp[2]) / pp[0];
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u32 df1 = f * (mod - nfra) / mod / pp[4];
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df = df0 - df1;
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} else {
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df = f * (nint) / pp[0];
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}
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df_quotient = df / m;
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df_remainder = ((df % m) * 1000) / m;
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if (freq > df_quotient) {
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df_quotient = freq - df_quotient - 1;
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df_remainder = 1000 - df_remainder;
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} else {
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df_quotient = df_quotient - freq;
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}
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if (df_quotient_min > df_quotient ||
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(df_quotient_min == df_quotient &&
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df_remainder_min > df_remainder)) {
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/* found a closer freq, save parameters */
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clk->p[SEL_FRA] = 1;
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clk->p[SDM_MOD] = sdm;
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clk->p[PH_SEL] = ph;
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clk->p[NFRA] = nfra;
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clk->p[DIVR] = r;
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clk->p[DIVM] = m;
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fout = df / m;
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df_quotient_min = df_quotient;
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df_remainder_min = df_remainder;
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}
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}
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}
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}
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if (!fout) {
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pr_err("%s: %s freq:%lu not found a valid setting\n",
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__func__, clk_hw_get_name(&clk->hw), freq);
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return -EINVAL;
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}
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return fout;
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}
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static long plltv_div(struct sp_pll *clk, unsigned long freq)
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{
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if (freq % 100)
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return plltv_fractional_div(clk, freq);
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return plltv_integer_div(clk, freq);
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}
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static int plltv_set_rate(struct sp_pll *clk)
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{
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unsigned long flags;
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u32 r0, r1, r2;
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r0 = BIT(clk->bp_bit + 16);
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r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);
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r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);
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r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);
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r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);
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r1 = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);
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r2 = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1);
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r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1);
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spin_lock_irqsave(&clk->lock, flags);
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writel(r0, clk->reg);
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writel(r1, clk->reg + 4);
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writel(r2, clk->reg + 8);
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spin_unlock_irqrestore(&clk->lock, flags);
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return 0;
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}
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/*********************************** PLL_A ***********************************/
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/* from Q628_PLLs_REG_setting.xlsx */
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static const struct {
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u32 rate;
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u32 regs[5];
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} pa[] = {
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{
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.rate = 135475200,
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.regs = {
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0x4801,
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0x02df,
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0x248f,
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0x0211,
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0x33e9
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}
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},
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{
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.rate = 147456000,
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.regs = {
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0x4801,
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0x1adf,
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0x2490,
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0x0349,
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0x33e9
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}
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},
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{
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.rate = 196608000,
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.regs = {
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0x4801,
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0x42ef,
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0x2495,
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0x01c6,
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0x33e9
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}
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},
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};
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static int plla_set_rate(struct sp_pll *clk)
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{
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const u32 *pp = pa[clk->p[0]].regs;
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unsigned long flags;
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int i;
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spin_lock_irqsave(&clk->lock, flags);
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for (i = 0; i < ARRAY_SIZE(pa->regs); i++)
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writel(0xffff0000 | pp[i], clk->reg + (i * 4));
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spin_unlock_irqrestore(&clk->lock, flags);
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return 0;
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}
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static long plla_round_rate(struct sp_pll *clk, unsigned long rate)
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{
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int i = ARRAY_SIZE(pa);
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while (--i) {
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if (rate >= pa[i].rate)
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break;
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}
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clk->p[0] = i;
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return pa[i].rate;
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}
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/********************************** SP_PLL ***********************************/
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static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate)
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{
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u32 fbdiv;
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u32 max = 1 << clk->div_width;
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fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate);
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if (fbdiv > max)
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fbdiv = max;
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return fbdiv;
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}
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static long sp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct sp_pll *clk = to_sp_pll(hw);
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long ret;
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if (rate == *prate) {
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ret = *prate; /* bypass */
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} else if (clk->div_width == DIV_A) {
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ret = plla_round_rate(clk, rate);
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} else if (clk->div_width == DIV_TV) {
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ret = plltv_div(clk, rate);
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if (ret < 0)
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ret = *prate;
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} else {
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ret = sp_pll_calc_div(clk, rate) * clk->brate;
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}
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return ret;
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}
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static unsigned long sp_pll_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct sp_pll *clk = to_sp_pll(hw);
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u32 reg = readl(clk->reg);
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unsigned long ret;
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if (reg & BIT(clk->bp_bit)) {
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ret = prate; /* bypass */
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} else if (clk->div_width == DIV_A) {
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ret = pa[clk->p[0]].rate;
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} else if (clk->div_width == DIV_TV) {
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u32 m, r, reg2;
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r = FIELD_GET(MASK_DIVR, readl(clk->reg + 4));
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reg2 = readl(clk->reg + 8);
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m = FIELD_GET(MASK_DIVM, reg2) + 1;
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if (reg & MASK_SEL_FRA) {
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/* fractional divider */
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u32 sdm = FIELD_GET(MASK_SDM_MOD, reg);
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u32 ph = FIELD_GET(MASK_PH_SEL, reg);
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u32 nfra = FIELD_GET(MASK_NFRA, reg);
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const u32 *pp = pt[ph];
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unsigned long r0, r1;
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ret = prate >> r;
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r0 = ret * (pp[1] + pp[2]) / pp[0];
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r1 = ret * (sdm_mod_vals[sdm] - nfra) / sdm_mod_vals[sdm] / pp[4];
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ret = (r0 - r1) / m;
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} else {
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/* integer divider */
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u32 n = FIELD_GET(MASK_DIVN, reg2) + 1;
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ret = (prate / m * n) >> r;
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}
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} else {
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u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1;
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ret = clk->brate * fbdiv;
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}
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return ret;
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}
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static int sp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct sp_pll *clk = to_sp_pll(hw);
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unsigned long flags;
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u32 reg;
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reg = BIT(clk->bp_bit + 16); /* HIWORD_MASK */
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if (rate == prate) {
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reg |= BIT(clk->bp_bit); /* bypass */
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} else if (clk->div_width == DIV_A) {
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return plla_set_rate(clk);
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} else if (clk->div_width == DIV_TV) {
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return plltv_set_rate(clk);
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} else if (clk->div_width) {
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u32 fbdiv = sp_pll_calc_div(clk, rate);
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u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift);
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reg |= mask << 16;
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reg |= ((fbdiv - 1) << clk->div_shift) & mask;
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}
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spin_lock_irqsave(&clk->lock, flags);
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writel(reg, clk->reg);
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spin_unlock_irqrestore(&clk->lock, flags);
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return 0;
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}
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static int sp_pll_enable(struct clk_hw *hw)
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{
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struct sp_pll *clk = to_sp_pll(hw);
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writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg);
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return 0;
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}
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static void sp_pll_disable(struct clk_hw *hw)
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{
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struct sp_pll *clk = to_sp_pll(hw);
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writel(BIT(clk->pd_bit + 16), clk->reg);
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}
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static int sp_pll_is_enabled(struct clk_hw *hw)
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{
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struct sp_pll *clk = to_sp_pll(hw);
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return readl(clk->reg) & BIT(clk->pd_bit);
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}
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static const struct clk_ops sp_pll_ops = {
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.enable = sp_pll_enable,
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.disable = sp_pll_disable,
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.is_enabled = sp_pll_is_enabled,
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.round_rate = sp_pll_round_rate,
|
|
.recalc_rate = sp_pll_recalc_rate,
|
|
.set_rate = sp_pll_set_rate
|
|
};
|
|
|
|
static const struct clk_ops sp_pll_sub_ops = {
|
|
.enable = sp_pll_enable,
|
|
.disable = sp_pll_disable,
|
|
.is_enabled = sp_pll_is_enabled,
|
|
.recalc_rate = sp_pll_recalc_rate,
|
|
};
|
|
|
|
static struct clk_hw *sp_pll_register(struct device *dev, const char *name,
|
|
const struct clk_parent_data *parent_data,
|
|
void __iomem *reg, int pd_bit, int bp_bit,
|
|
unsigned long brate, int shift, int width,
|
|
unsigned long flags)
|
|
{
|
|
struct sp_pll *pll;
|
|
struct clk_hw *hw;
|
|
struct clk_init_data initd = {
|
|
.name = name,
|
|
.parent_data = parent_data,
|
|
.ops = (bp_bit >= 0) ? &sp_pll_ops : &sp_pll_sub_ops,
|
|
.num_parents = 1,
|
|
.flags = flags,
|
|
};
|
|
int ret;
|
|
|
|
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
|
|
if (!pll)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
pll->hw.init = &initd;
|
|
pll->reg = reg;
|
|
pll->pd_bit = pd_bit;
|
|
pll->bp_bit = bp_bit;
|
|
pll->brate = brate;
|
|
pll->div_shift = shift;
|
|
pll->div_width = width;
|
|
spin_lock_init(&pll->lock);
|
|
|
|
hw = &pll->hw;
|
|
ret = devm_clk_hw_register(dev, hw);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
return hw;
|
|
}
|
|
|
|
#define PLLA_CTL (pll_base + 0x1c)
|
|
#define PLLE_CTL (pll_base + 0x30)
|
|
#define PLLF_CTL (pll_base + 0x34)
|
|
#define PLLTV_CTL (pll_base + 0x38)
|
|
|
|
static int sp7021_clk_probe(struct platform_device *pdev)
|
|
{
|
|
static const u32 sp_clken[] = {
|
|
0x67ef, 0x03ff, 0xff03, 0xfff0, 0x0004, /* G0.1~5 */
|
|
0x0000, 0x8000, 0xffff, 0x0040, 0x0000, /* G0.6~10 */
|
|
};
|
|
static struct clk_parent_data pd_ext, pd_sys, pd_e;
|
|
struct device *dev = &pdev->dev;
|
|
void __iomem *clk_base, *pll_base, *sys_base;
|
|
struct clk_hw_onecell_data *clk_data;
|
|
struct clk_hw **hws;
|
|
int i;
|
|
|
|
clk_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(clk_base))
|
|
return PTR_ERR(clk_base);
|
|
pll_base = devm_platform_ioremap_resource(pdev, 1);
|
|
if (IS_ERR(pll_base))
|
|
return PTR_ERR(pll_base);
|
|
sys_base = devm_platform_ioremap_resource(pdev, 2);
|
|
if (IS_ERR(sys_base))
|
|
return PTR_ERR(sys_base);
|
|
|
|
/* enable default clks */
|
|
for (i = 0; i < ARRAY_SIZE(sp_clken); i++)
|
|
writel((sp_clken[i] << 16) | sp_clken[i], clk_base + i * 4);
|
|
|
|
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_MAX),
|
|
GFP_KERNEL);
|
|
if (!clk_data)
|
|
return -ENOMEM;
|
|
clk_data->num = CLK_MAX;
|
|
|
|
hws = clk_data->hws;
|
|
pd_ext.index = 0;
|
|
|
|
/* PLLs */
|
|
hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL,
|
|
11, 12, 27000000, 0, DIV_A, 0);
|
|
if (IS_ERR(hws[PLL_A]))
|
|
return PTR_ERR(hws[PLL_A]);
|
|
|
|
hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL,
|
|
6, 2, 50000000, 0, 0, 0);
|
|
if (IS_ERR(hws[PLL_E]))
|
|
return PTR_ERR(hws[PLL_E]);
|
|
pd_e.hw = hws[PLL_E];
|
|
hws[PLL_E_2P5] = sp_pll_register(dev, "plle_2p5", &pd_e, PLLE_CTL,
|
|
13, -1, 2500000, 0, 0, 0);
|
|
if (IS_ERR(hws[PLL_E_2P5]))
|
|
return PTR_ERR(hws[PLL_E_2P5]);
|
|
hws[PLL_E_25] = sp_pll_register(dev, "plle_25", &pd_e, PLLE_CTL,
|
|
12, -1, 25000000, 0, 0, 0);
|
|
if (IS_ERR(hws[PLL_E_25]))
|
|
return PTR_ERR(hws[PLL_E_25]);
|
|
hws[PLL_E_112P5] = sp_pll_register(dev, "plle_112p5", &pd_e, PLLE_CTL,
|
|
11, -1, 112500000, 0, 0, 0);
|
|
if (IS_ERR(hws[PLL_E_112P5]))
|
|
return PTR_ERR(hws[PLL_E_112P5]);
|
|
|
|
hws[PLL_F] = sp_pll_register(dev, "pllf", &pd_ext, PLLF_CTL,
|
|
0, 10, 13500000, 1, 4, 0);
|
|
if (IS_ERR(hws[PLL_F]))
|
|
return PTR_ERR(hws[PLL_F]);
|
|
|
|
hws[PLL_TV] = sp_pll_register(dev, "plltv", &pd_ext, PLLTV_CTL,
|
|
0, 15, 27000000, 0, DIV_TV, 0);
|
|
if (IS_ERR(hws[PLL_TV]))
|
|
return PTR_ERR(hws[PLL_TV]);
|
|
hws[PLL_TV_A] = devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0,
|
|
PLLTV_CTL + 4, 5, 1,
|
|
CLK_DIVIDER_POWER_OF_TWO,
|
|
&to_sp_pll(hws[PLL_TV])->lock);
|
|
if (IS_ERR(hws[PLL_TV_A]))
|
|
return PTR_ERR(hws[PLL_TV_A]);
|
|
|
|
/* system clock, should not be disabled */
|
|
hws[PLL_SYS] = sp_pll_register(dev, "pllsys", &pd_ext, sys_base,
|
|
10, 9, 13500000, 0, 4, CLK_IS_CRITICAL);
|
|
if (IS_ERR(hws[PLL_SYS]))
|
|
return PTR_ERR(hws[PLL_SYS]);
|
|
pd_sys.hw = hws[PLL_SYS];
|
|
|
|
/* gates */
|
|
for (i = 0; i < ARRAY_SIZE(sp_clk_gates); i++) {
|
|
char name[10];
|
|
u32 j = sp_clk_gates[i].reg;
|
|
struct clk_parent_data *pd = sp_clk_gates[i].ext_parent ? &pd_ext : &pd_sys;
|
|
|
|
sprintf(name, "%02d_0x%02x", i, j);
|
|
hws[i] = devm_clk_hw_register_gate_parent_data(dev, name, pd, 0,
|
|
clk_base + (j >> 4) * 4,
|
|
j & 0x0f,
|
|
CLK_GATE_HIWORD_MASK,
|
|
NULL);
|
|
if (IS_ERR(hws[i]))
|
|
return PTR_ERR(hws[i]);
|
|
}
|
|
|
|
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
|
|
}
|
|
|
|
static const struct of_device_id sp7021_clk_dt_ids[] = {
|
|
{ .compatible = "sunplus,sp7021-clkc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sp7021_clk_dt_ids);
|
|
|
|
static struct platform_driver sp7021_clk_driver = {
|
|
.probe = sp7021_clk_probe,
|
|
.driver = {
|
|
.name = "sp7021-clk",
|
|
.of_match_table = sp7021_clk_dt_ids,
|
|
},
|
|
};
|
|
module_platform_driver(sp7021_clk_driver);
|
|
|
|
MODULE_AUTHOR("Sunplus Technology");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Clock driver for Sunplus SP7021 SoC");
|