766 lines
16 KiB
C
766 lines
16 KiB
C
/*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "DPI"
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/string.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <linux/sys_soc.h>
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#include "omapdss.h"
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#include "dss.h"
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struct dpi_data {
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struct platform_device *pdev;
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enum dss_model dss_model;
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struct dss_device *dss;
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unsigned int id;
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struct regulator *vdds_dsi_reg;
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enum dss_clk_source clk_src;
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struct dss_pll *pll;
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struct mutex lock;
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struct videomode vm;
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struct dss_lcd_mgr_config mgr_config;
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int data_lines;
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struct omap_dss_device output;
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};
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static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev)
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{
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return container_of(dssdev, struct dpi_data, output);
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}
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static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi,
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enum omap_channel channel)
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{
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/*
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* Possible clock sources:
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* LCD1: FCK/PLL1_1/HDMI_PLL
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* LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3)
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* LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1)
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*/
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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{
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if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1))
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return DSS_CLK_SRC_PLL1_1;
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break;
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}
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case OMAP_DSS_CHANNEL_LCD2:
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{
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if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
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return DSS_CLK_SRC_PLL1_3;
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if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3))
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return DSS_CLK_SRC_PLL2_3;
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break;
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}
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case OMAP_DSS_CHANNEL_LCD3:
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{
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if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1))
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return DSS_CLK_SRC_PLL2_1;
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if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
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return DSS_CLK_SRC_PLL1_3;
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break;
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}
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default:
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break;
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}
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return DSS_CLK_SRC_FCK;
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}
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static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
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{
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enum omap_channel channel = dpi->output.dispc_channel;
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/*
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* XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
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* would also be used for DISPC fclk. Meaning, when the DPI output is
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* disabled, DISPC clock will be disabled, and TV out will stop.
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*/
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switch (dpi->dss_model) {
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case DSS_MODEL_OMAP2:
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case DSS_MODEL_OMAP3:
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return DSS_CLK_SRC_FCK;
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case DSS_MODEL_OMAP4:
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return DSS_CLK_SRC_PLL1_1;
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case OMAP_DSS_CHANNEL_LCD2:
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return DSS_CLK_SRC_PLL2_1;
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default:
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return DSS_CLK_SRC_FCK;
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}
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case DSS_MODEL_OMAP5:
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return DSS_CLK_SRC_PLL1_1;
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case OMAP_DSS_CHANNEL_LCD3:
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return DSS_CLK_SRC_PLL2_1;
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case OMAP_DSS_CHANNEL_LCD2:
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default:
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return DSS_CLK_SRC_FCK;
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}
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case DSS_MODEL_DRA7:
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return dpi_get_clk_src_dra7xx(dpi, channel);
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default:
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return DSS_CLK_SRC_FCK;
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}
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}
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struct dpi_clk_calc_ctx {
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struct dpi_data *dpi;
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unsigned int clkout_idx;
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/* inputs */
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unsigned long pck_min, pck_max;
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/* outputs */
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struct dss_pll_clock_info pll_cinfo;
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unsigned long fck;
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struct dispc_clock_info dispc_cinfo;
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};
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static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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unsigned long pck, void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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/*
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* Odd dividers give us uneven duty cycle, causing problem when level
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* shifted. So skip all odd dividers when the pixel clock is on the
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* higher side.
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*/
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if (ctx->pck_min >= 100000000) {
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if (lckd > 1 && lckd % 2 != 0)
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return false;
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if (pckd > 1 && pckd % 2 != 0)
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return false;
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}
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ctx->dispc_cinfo.lck_div = lckd;
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ctx->dispc_cinfo.pck_div = pckd;
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ctx->dispc_cinfo.lck = lck;
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ctx->dispc_cinfo.pck = pck;
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return true;
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}
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static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
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void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
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ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
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return dispc_div_calc(ctx->dpi->dss->dispc, dispc,
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ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
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unsigned long clkdco,
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void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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ctx->pll_cinfo.n = n;
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ctx->pll_cinfo.m = m;
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ctx->pll_cinfo.fint = fint;
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ctx->pll_cinfo.clkdco = clkdco;
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return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
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ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss),
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dpi_calc_hsdiv_cb, ctx);
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}
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static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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ctx->fck = fck;
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return dispc_div_calc(ctx->dpi->dss->dispc, fck,
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ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
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struct dpi_clk_calc_ctx *ctx)
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{
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unsigned long clkin;
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memset(ctx, 0, sizeof(*ctx));
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ctx->dpi = dpi;
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ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src);
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clkin = clk_get_rate(dpi->pll->clkin);
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if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
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unsigned long pll_min, pll_max;
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ctx->pck_min = pck - 1000;
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ctx->pck_max = pck + 1000;
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pll_min = 0;
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pll_max = 0;
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return dss_pll_calc_a(ctx->dpi->pll, clkin,
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pll_min, pll_max,
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dpi_calc_pll_cb, ctx);
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} else { /* DSS_PLL_TYPE_B */
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dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
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ctx->dispc_cinfo.lck_div = 1;
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ctx->dispc_cinfo.pck_div = 1;
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ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0];
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ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck;
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return true;
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}
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}
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static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck,
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struct dpi_clk_calc_ctx *ctx)
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{
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int i;
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/*
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* DSS fck gives us very few possibilities, so finding a good pixel
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* clock may not be possible. We try multiple times to find the clock,
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* each time widening the pixel clock range we look for, up to
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* +/- ~15MHz.
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*/
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for (i = 0; i < 25; ++i) {
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bool ok;
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memset(ctx, 0, sizeof(*ctx));
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ctx->dpi = dpi;
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if (pck > 1000 * i * i * i)
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ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
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else
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ctx->pck_min = 0;
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ctx->pck_max = pck + 1000 * i * i * i;
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ok = dss_div_calc(dpi->dss, pck, ctx->pck_min,
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dpi_calc_dss_cb, ctx);
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if (ok)
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return ok;
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}
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return false;
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}
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static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel,
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unsigned long pck_req, unsigned long *fck, int *lck_div,
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int *pck_div)
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{
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struct dpi_clk_calc_ctx ctx;
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int r;
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bool ok;
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ok = dpi_pll_clk_calc(dpi, pck_req, &ctx);
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if (!ok)
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return -EINVAL;
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r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
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if (r)
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return r;
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dss_select_lcd_clk_source(dpi->dss, channel, dpi->clk_src);
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dpi->mgr_config.clock_info = ctx.dispc_cinfo;
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*fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
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*lck_div = ctx.dispc_cinfo.lck_div;
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*pck_div = ctx.dispc_cinfo.pck_div;
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return 0;
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}
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static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
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unsigned long *fck, int *lck_div, int *pck_div)
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{
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struct dpi_clk_calc_ctx ctx;
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int r;
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bool ok;
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ok = dpi_dss_clk_calc(dpi, pck_req, &ctx);
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if (!ok)
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return -EINVAL;
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r = dss_set_fck_rate(dpi->dss, ctx.fck);
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if (r)
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return r;
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dpi->mgr_config.clock_info = ctx.dispc_cinfo;
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*fck = ctx.fck;
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*lck_div = ctx.dispc_cinfo.lck_div;
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*pck_div = ctx.dispc_cinfo.pck_div;
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return 0;
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}
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static int dpi_set_mode(struct dpi_data *dpi)
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{
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const struct videomode *vm = &dpi->vm;
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int lck_div = 0, pck_div = 0;
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unsigned long fck = 0;
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int r = 0;
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if (dpi->pll)
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r = dpi_set_pll_clk(dpi, dpi->output.dispc_channel,
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vm->pixelclock, &fck, &lck_div, &pck_div);
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else
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r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck,
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&lck_div, &pck_div);
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if (r)
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return r;
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return 0;
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}
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static void dpi_config_lcd_manager(struct dpi_data *dpi)
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{
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dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
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dpi->mgr_config.stallmode = false;
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dpi->mgr_config.fifohandcheck = false;
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dpi->mgr_config.video_port_width = dpi->data_lines;
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dpi->mgr_config.lcden_sig_polarity = 0;
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dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config);
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}
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static int dpi_display_enable(struct omap_dss_device *dssdev)
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{
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struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
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struct omap_dss_device *out = &dpi->output;
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int r;
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mutex_lock(&dpi->lock);
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if (!out->dispc_channel_connected) {
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DSSERR("failed to enable display: no output/manager\n");
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r = -ENODEV;
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goto err_no_out_mgr;
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}
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if (dpi->vdds_dsi_reg) {
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r = regulator_enable(dpi->vdds_dsi_reg);
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if (r)
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goto err_reg_enable;
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}
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r = dispc_runtime_get(dpi->dss->dispc);
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if (r)
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goto err_get_dispc;
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r = dss_dpi_select_source(dpi->dss, dpi->id, out->dispc_channel);
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if (r)
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goto err_src_sel;
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if (dpi->pll) {
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r = dss_pll_enable(dpi->pll);
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if (r)
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goto err_pll_init;
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}
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r = dpi_set_mode(dpi);
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if (r)
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goto err_set_mode;
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dpi_config_lcd_manager(dpi);
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mdelay(2);
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r = dss_mgr_enable(&dpi->output);
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if (r)
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goto err_mgr_enable;
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mutex_unlock(&dpi->lock);
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return 0;
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err_mgr_enable:
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err_set_mode:
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if (dpi->pll)
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dss_pll_disable(dpi->pll);
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err_pll_init:
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err_src_sel:
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dispc_runtime_put(dpi->dss->dispc);
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err_get_dispc:
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if (dpi->vdds_dsi_reg)
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regulator_disable(dpi->vdds_dsi_reg);
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err_reg_enable:
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err_no_out_mgr:
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mutex_unlock(&dpi->lock);
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return r;
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}
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static void dpi_display_disable(struct omap_dss_device *dssdev)
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{
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struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
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mutex_lock(&dpi->lock);
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dss_mgr_disable(&dpi->output);
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if (dpi->pll) {
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dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
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DSS_CLK_SRC_FCK);
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dss_pll_disable(dpi->pll);
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}
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dispc_runtime_put(dpi->dss->dispc);
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|
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if (dpi->vdds_dsi_reg)
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regulator_disable(dpi->vdds_dsi_reg);
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|
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mutex_unlock(&dpi->lock);
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}
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|
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static void dpi_set_timings(struct omap_dss_device *dssdev,
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const struct videomode *vm)
|
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{
|
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struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
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DSSDBG("dpi_set_timings\n");
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mutex_lock(&dpi->lock);
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dpi->vm = *vm;
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|
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mutex_unlock(&dpi->lock);
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}
|
|
|
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static int dpi_check_timings(struct omap_dss_device *dssdev,
|
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struct videomode *vm)
|
|
{
|
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struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
|
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int lck_div, pck_div;
|
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unsigned long fck;
|
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unsigned long pck;
|
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struct dpi_clk_calc_ctx ctx;
|
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bool ok;
|
|
|
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if (vm->hactive % 8 != 0)
|
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return -EINVAL;
|
|
|
|
if (vm->pixelclock == 0)
|
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return -EINVAL;
|
|
|
|
if (dpi->pll) {
|
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ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx);
|
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if (!ok)
|
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return -EINVAL;
|
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|
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fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
|
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} else {
|
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ok = dpi_dss_clk_calc(dpi, vm->pixelclock, &ctx);
|
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if (!ok)
|
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return -EINVAL;
|
|
|
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fck = ctx.fck;
|
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}
|
|
|
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lck_div = ctx.dispc_cinfo.lck_div;
|
|
pck_div = ctx.dispc_cinfo.pck_div;
|
|
|
|
pck = fck / lck_div / pck_div;
|
|
|
|
vm->pixelclock = pck;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dpi_verify_pll(struct dss_pll *pll)
|
|
{
|
|
int r;
|
|
|
|
/* do initial setup with the PLL to see if it is operational */
|
|
|
|
r = dss_pll_enable(pll);
|
|
if (r)
|
|
return r;
|
|
|
|
dss_pll_disable(pll);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dpi_init_pll(struct dpi_data *dpi)
|
|
{
|
|
struct dss_pll *pll;
|
|
|
|
if (dpi->pll)
|
|
return;
|
|
|
|
dpi->clk_src = dpi_get_clk_src(dpi);
|
|
|
|
pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
|
|
if (!pll)
|
|
return;
|
|
|
|
if (dpi_verify_pll(pll)) {
|
|
DSSWARN("PLL not operational\n");
|
|
return;
|
|
}
|
|
|
|
dpi->pll = pll;
|
|
}
|
|
|
|
/*
|
|
* Return a hardcoded channel for the DPI output. This should work for
|
|
* current use cases, but this can be later expanded to either resolve
|
|
* the channel in some more dynamic manner, or get the channel as a user
|
|
* parameter.
|
|
*/
|
|
static enum omap_channel dpi_get_channel(struct dpi_data *dpi)
|
|
{
|
|
switch (dpi->dss_model) {
|
|
case DSS_MODEL_OMAP2:
|
|
case DSS_MODEL_OMAP3:
|
|
return OMAP_DSS_CHANNEL_LCD;
|
|
|
|
case DSS_MODEL_DRA7:
|
|
switch (dpi->id) {
|
|
case 2:
|
|
return OMAP_DSS_CHANNEL_LCD3;
|
|
case 1:
|
|
return OMAP_DSS_CHANNEL_LCD2;
|
|
case 0:
|
|
default:
|
|
return OMAP_DSS_CHANNEL_LCD;
|
|
}
|
|
|
|
case DSS_MODEL_OMAP4:
|
|
return OMAP_DSS_CHANNEL_LCD2;
|
|
|
|
case DSS_MODEL_OMAP5:
|
|
return OMAP_DSS_CHANNEL_LCD3;
|
|
|
|
default:
|
|
DSSWARN("unsupported DSS version\n");
|
|
return OMAP_DSS_CHANNEL_LCD;
|
|
}
|
|
}
|
|
|
|
static int dpi_connect(struct omap_dss_device *src,
|
|
struct omap_dss_device *dst)
|
|
{
|
|
struct dpi_data *dpi = dpi_get_data_from_dssdev(dst);
|
|
int r;
|
|
|
|
dpi_init_pll(dpi);
|
|
|
|
r = omapdss_device_connect(dst->dss, dst, dst->next);
|
|
if (r)
|
|
return r;
|
|
|
|
dst->dispc_channel_connected = true;
|
|
return 0;
|
|
}
|
|
|
|
static void dpi_disconnect(struct omap_dss_device *src,
|
|
struct omap_dss_device *dst)
|
|
{
|
|
dst->dispc_channel_connected = false;
|
|
|
|
omapdss_device_disconnect(dst, dst->next);
|
|
}
|
|
|
|
static const struct omap_dss_device_ops dpi_ops = {
|
|
.connect = dpi_connect,
|
|
.disconnect = dpi_disconnect,
|
|
|
|
.enable = dpi_display_enable,
|
|
.disable = dpi_display_disable,
|
|
|
|
.check_timings = dpi_check_timings,
|
|
.set_timings = dpi_set_timings,
|
|
};
|
|
|
|
static int dpi_init_output_port(struct dpi_data *dpi, struct device_node *port)
|
|
{
|
|
struct omap_dss_device *out = &dpi->output;
|
|
u32 port_num = 0;
|
|
int r;
|
|
|
|
of_property_read_u32(port, "reg", &port_num);
|
|
dpi->id = port_num <= 2 ? port_num : 0;
|
|
|
|
switch (port_num) {
|
|
case 2:
|
|
out->name = "dpi.2";
|
|
break;
|
|
case 1:
|
|
out->name = "dpi.1";
|
|
break;
|
|
case 0:
|
|
default:
|
|
out->name = "dpi.0";
|
|
break;
|
|
}
|
|
|
|
out->dev = &dpi->pdev->dev;
|
|
out->id = OMAP_DSS_OUTPUT_DPI;
|
|
out->output_type = OMAP_DISPLAY_TYPE_DPI;
|
|
out->dispc_channel = dpi_get_channel(dpi);
|
|
out->of_ports = BIT(port_num);
|
|
out->ops = &dpi_ops;
|
|
out->owner = THIS_MODULE;
|
|
|
|
out->next = omapdss_of_find_connected_device(out->dev->of_node, 0);
|
|
if (IS_ERR(out->next)) {
|
|
if (PTR_ERR(out->next) != -EPROBE_DEFER)
|
|
dev_err(out->dev, "failed to find video sink\n");
|
|
return PTR_ERR(out->next);
|
|
}
|
|
|
|
r = omapdss_output_validate(out);
|
|
if (r) {
|
|
omapdss_device_put(out->next);
|
|
out->next = NULL;
|
|
return r;
|
|
}
|
|
|
|
omapdss_device_register(out);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dpi_uninit_output_port(struct device_node *port)
|
|
{
|
|
struct dpi_data *dpi = port->data;
|
|
struct omap_dss_device *out = &dpi->output;
|
|
|
|
if (out->next)
|
|
omapdss_device_put(out->next);
|
|
omapdss_device_unregister(out);
|
|
}
|
|
|
|
static const struct soc_device_attribute dpi_soc_devices[] = {
|
|
{ .machine = "OMAP3[456]*" },
|
|
{ .machine = "[AD]M37*" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int dpi_init_regulator(struct dpi_data *dpi)
|
|
{
|
|
struct regulator *vdds_dsi;
|
|
|
|
/*
|
|
* The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and
|
|
* DM37xx only.
|
|
*/
|
|
if (!soc_device_match(dpi_soc_devices))
|
|
return 0;
|
|
|
|
vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
|
|
if (IS_ERR(vdds_dsi)) {
|
|
if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
|
|
DSSERR("can't get VDDS_DSI regulator\n");
|
|
return PTR_ERR(vdds_dsi);
|
|
}
|
|
|
|
dpi->vdds_dsi_reg = vdds_dsi;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
|
|
struct device_node *port, enum dss_model dss_model)
|
|
{
|
|
struct dpi_data *dpi;
|
|
struct device_node *ep;
|
|
u32 datalines;
|
|
int r;
|
|
|
|
dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
|
|
if (!dpi)
|
|
return -ENOMEM;
|
|
|
|
ep = of_get_next_child(port, NULL);
|
|
if (!ep)
|
|
return 0;
|
|
|
|
r = of_property_read_u32(ep, "data-lines", &datalines);
|
|
of_node_put(ep);
|
|
if (r) {
|
|
DSSERR("failed to parse datalines\n");
|
|
return r;
|
|
}
|
|
|
|
dpi->data_lines = datalines;
|
|
|
|
dpi->pdev = pdev;
|
|
dpi->dss_model = dss_model;
|
|
dpi->dss = dss;
|
|
port->data = dpi;
|
|
|
|
mutex_init(&dpi->lock);
|
|
|
|
r = dpi_init_regulator(dpi);
|
|
if (r)
|
|
return r;
|
|
|
|
return dpi_init_output_port(dpi, port);
|
|
}
|
|
|
|
void dpi_uninit_port(struct device_node *port)
|
|
{
|
|
struct dpi_data *dpi = port->data;
|
|
|
|
if (!dpi)
|
|
return;
|
|
|
|
dpi_uninit_output_port(port);
|
|
}
|